AD9520-4 Analog Devices, Inc., AD9520-4 Datasheet - Page 78

• Manufacturer Part Number: AD9520-4
• Description: 12 Lvpecl/24 Cmos Output Clock Generator With Integrated 1.6 Ghz Vco
• Manufacturer: Analog Devices, Inc.

Reg.
Addr
(Hex) Bit(s) Name
197
197
197
197
198
198
198
199
199
19A
19A
19A
19A
19A
19B
19B
AD9520-4
[6]
[5]
[4]
[3:0]
[2]
[1]
[0]
[7:4]
[3:0]
[7]
[6]
[5]
[4]
[3:0]
[2]
[1]
Divider 2 ignore SYNC
Divider 2 force high
Divider 2 start high
Divider 2 phase offset
Channel 2 power-down
Channel 2 direct-to-output
Disable Divider 2 DCC
Divider 3 low cycles
Divider 3 high cycles
Divider 3 bypass
Divider 3 ignore SYNC
Divider 3 force high
Divider 3 start high
Divider 3 phase offset
Channel 3 power-down
Channel 3 direct-to-output
Description
No SYNC.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
Forces divider output to high. This requires that no SYNC also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
Phase offset.
Channel 2 power-down.
[2] = 0; normal operation (default).
[2] = 1; powered down. (OUT6/OUT6, OUT7/OUT7, and OUT8/OUT8 are put into safe power-
down mode by setting this bit.)
Connects OUT6, OUT7, and OUT8 to Divider 2 or directly to VCO or CLK.
[1] = 0; OUT6, OUT7 and OUT8 are connected to Divider 2 (default).
[1] = 1:
If 0x1E1[1:0] = 10b, the VCO is routed directly to OUT6, OUT7, and OUT8.
If 0x1E1[1:0] = 00b, the CLK is routed directly to OUT6, OUT7, and OUT8.
If 0x1E1[1:0] = 01b, there is no effect.
Duty-cycle correction function.
[0] = 0; enable duty-cycle correction (default).
[0] = 1; disable duty-cycle correction.
Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x0 means the divider is low for one input clock cycle (default: 0x0).
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x0 means the divider is high for one input clock cycle (default: 0x0).
Bypasses and powers down the divider; routes input to divider output.
[7] = 0; use divider (default).
[7] = 1; bypass divider.
No SYNC.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
Forces divider output to high. This requires that no SYNC also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
Phase offset (default: 0x0).
Channel 3 power-down.
[2] = 0; normal operation (default).
[2] = 1; powered down. (OUT9/OUT9, OUT10/OUT10, and OUT11/OUT11 are also put into
safe power-down mode by setting this bit.)
Connects OUT9, OUT10, and OUT11 to Divider 3 or directly to VCO or CLK.
[1] = 0; OUT9, OUT10, and OUT11 are connected to Divider 3 (default).
[1] = 1:
If 0x1E1[1:0] = 10b, the VCO is routed directly to OUT9, OUT10, and OUT11.
If 0x1E1[1:0] = 00b, the CLK is routed directly to OUT9, OUT10, and OUT11.
If 0x1E1[1:0] = 01b, there is no effect.
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