ad6437 Analog Devices, Inc., ad6437 Datasheet
ad6437
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ad6437 Summary of contents
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... PGA and filters. The filters are software configurable for both the CO and RT modes. There is an auxiliary 7-bit auxiliary DAC (e.g., for timing recovery). The AD6437 has been designed to be versatile, and most blocks can be used or externally bypassed. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. ...
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... AD6437–SPECIFICATIONS Parameter TRANSMIT CHANNEL SNR THD DAC Resolution Sample Rate Data Format Output Compliance Range TRANSMIT FILTER Input Voltage Range Input Impedance Output Voltage Range CO Mode 3 dB Frequency Stopband Rejection @ 16 MHz Passband Passband Gain RT Mode 3 dB Frequency Stopband Rejection @ 2.07 MHz ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6437 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Digital Output (Receive) Data from ADC. ADC Clock Input Sampled on Positive Edge. PIN CONFIGURATION PIN 1 2 IDENTIFIER TX13 7 TX12 8 TX11 9 AD6437 TX10 10 TOP VIEW TX9 11 (Not to Scale) TX8 12 TX7 13 TX6 14 TX5 15 TX4 16 TX3 17 TX2 18 TX1 19 ...
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... B). Typically, it will then be connected to TXLPF for the on-chip reconstruction filter (4th order Butterworth active filter). However, this filter can be bypassed if a different filter is required (e.g., to use the AD6437 in a non- standard application). The filter can be switched between two corner frequencies, for use in CO mode or RT mode. For downstream operation (CO mode), the band ends at 1.1 MHz and the filter’ ...
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... The filter capacitors shown in Figure 2 are used to decouple the internal reference voltages of the ADC. A buffer is required after the filters, at the input to the ADC. This must be able to drive the 30 pF input capacitance of the ADC, with the desired bandwidth and distortion properties. A typical part is the AD8042. AD6437 0 ...
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... SFRAME are clocked into the DSP Interface block on a falling edge of SCLK. The DSP interface decodes the first three bits of the incoming data word to determine if the AD6437 is being addressed. If the DSP has selected the AD6437, the next 10 bits are accepted. The first two bits decode one of four inter- nal data registers (Reg A, Reg B, Reg C, and Reg D), and the following eight bits used as data to be loaded into that register ...
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... AD6437 SDATA [2:0] Determines if AD6437 is selected, Addr 101 is assigned for AD6437. NOTE Data is transmitted in 13-bit words: SDATA 0, LSB, transmitted first; SDATA 12, MSB, transmitted last. TIMING RECEIVE INTERFACE The analog input is sampled every the rising edge of the ADC clock (RX_CLK), with digital data (RX11:RX0) being valid on each falling edge of RX_CLK ...
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... CONNECTION AND APPLICATION INFORMATION Decoupling All the internal bias points of the AD6437 DAC and ADC are decoupled as shown in Figures 2 and 3. All AD6437 power pins should be decoupled with tantalum capacitor and a parallel 0.1 F ceramic chip cap. The 0.1 F capacitors should be placed as closely as possible to the device pins. This configuration ensures a low impedance power source over a wide band of frequencies. ...
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... AD6437 This Material Copyrighted By Its Respective Manufacturer OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 80-Lead Plastic Quad Flatpack (PQFP) (S-80A) 0.690 (17.45) 0.667 (16.95) 0.555 (14.10) 0.134 (3.40) MAX 0.547 (13.90) 0.486 (12.35) BSC 0.041 (1.03) 0.029 (0.73 SEATING PLANE TOP VIEW (PINS DOWN) 0.004 (0.10) 20 MAX 21 0.010 (0.25) MIN 0.026 (0.65) ...
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This Material Copyrighted By Its Respective Manufacturer –11– ...
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This Material Copyrighted By Its Respective Manufacturer –12– ...