AD9520-5/PCBZ Analog Devices Inc, AD9520-5/PCBZ Datasheet - Page 7

• Manufacturer Part Number: AD9520-5/PCBZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc

Specifications of AD9520-5/PCBZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: AD9520-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Compliant

CLOCK INPUTS
Table 3.
Parameter
CLOCK INPUTS (CLK, CLK)
1
CLOCK OUTPUTS
Table 4.
Parameter
LVPECL CLOCK OUTPUTS
CMOS CLOCK OUTPUTS
Below about 1 MHz, the input should be dc-coupled. Care should be taken to match V
OUT0, OUT1, OUT2, OUT3,
Input Frequency
Input Sensitivity, Differential
Input Level, Differential
Input Common-Mode Voltage, V
Input Common-Mode Range, V
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
OUT0A, OUT0B, OUT1A, OUT1B,
OUT4, OUT5, OUT6, OUT7,
OUT8, OUT9, OUT10, OUT11
Output Frequency, Maximum
Output High Voltage, V
Output Low Voltage, V
Output Differential Voltage, V
OUT2A, OUT2B, OUT3A, OUT3B,
OUT4A, OUT4B, OUT5A, OUT5B,
OUT6A, OUT6B, OUT7A, OUT7B,
OUT8A, OUT8B, OUT9A, OUT9B,
OUT10A, OUT10B, OUT11A,
OUT11B
Output Frequency
Output Voltage High, V
Output Voltage Low, V
Output Voltage High, V
Output Voltage Low, V
Output Voltage High, V
Output Voltage Low, V
OL
OL
OL
OL
OH
OH
OH
OH
CMR
OD
CM
Min
2400
VS_DRV − 1.07
VS_DRV − 1.95
660
VS − 0.1
2.7
1.8
Min
0
0
1.3
1.3
3.9
1
1
Typ
150
1.57
150
4.7
2
Typ
VS_DRV − 0.96
VS_DRV − 1.79
820
Max
2.4
1.6
2
1.8
1.8
5.7
Rev. 0 | Page 7 of 80
Unit
GHz
GHz
mV p-p
V p-p
V
V
mV p-p
kΩ
pF
CM
.
Max
VS_DRV − 0.84
VS_DRV − 1.64
950
250
0.1
0.5
0.6
Test Conditions/Comments
Differential input
High frequency distribution (VCO divider)
Distribution only (VCO divider bypassed); this is the
frequency range supported by the channel divider
Measured at 2.4 GHz; jitter performance is improved with
slew rates > 1 V/ns
Larger voltage swings can turn on the protection diodes
and can degrade jitter performance
Self-biased; enables ac coupling
With 200 mV p-p signal applied; dc-coupled
CLK ac-coupled; CLK ac-bypassed to RF ground
Self-biased
Unit
V
V
MHz
V
V
mV
MHz
V
V
V
V
Test Conditions/Comments
Termination = 50 Ω to VS_DRV − 2 V
Differential (OUT, OUT)
Using direct to output; see Figure 17
(higher frequencies are possible, but
amplitude will not meet the V
specification); the maximum output
frequency is limited by the maximum
frequency at the CLK inputs
Single-ended; termination = 10 pF
See Figure 18
@ 1 mA load, VS_DRV = 3.3 V/2.5 V
@ 1 mA load, VS_DRV = 3.3 V/2.5 V
@ 10 mA load, VS_DRV = 3.3 V
@ 10 mA load, VS_DRV = 3.3 V
@ 10 mA load, VS_DRV = 2.5 V
@ 10 mA load, VS_DRV = 2.5 V
AD9520-5
OD