AD9600BCPZ-105 Analog Devices Inc, AD9600BCPZ-105 Datasheet - Page 36

• Manufacturer Part Number: AD9600BCPZ-105
• Description: IC,A/D CONVERTER,DUAL,10-BIT,CMOS,LLCC,64PIN
• Manufacturer: Analog Devices Inc

Specifications of AD9600BCPZ-105

• Number Of Bits: 10
• Sampling Rate (per Second): 105M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 650mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9600
BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD9600 includes built-in test features to enable verification
of the integrity of each channel as well as to facilitate board level
debugging. A BIST feature is included that verifies the integrity
of the digital datapath of the AD9600. Various output test options
are also provided to place predictable values on the outputs of
the AD9600.
BUILT-IN SELF-TEST (BIST)
The BIST is a thorough test of the digital portion of the selected
AD9600 signal path. When enabled, the test runs from an internal
pseudorandom noise (PN) source through the digital datapath,
starting at the ADC block output. The BIST sequence runs for
512 cycles and then stops. The BIST signature value for Channel
A or Channel B is placed in Register 0x24 and Register 0x25. If
one channel is chosen, its BIST signature is written to the two
registers. If both channels are chosen, the results of the two
channels are XOR’ e d and placed in the BIST signature registers.
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The outputs are not disconnected during this test; therefore, the PN
sequence can be observed as it runs. The PN sequence can be
continued from its last value or started from the beginning, based
on the value programmed in Bit 2 of Register 0x0E. The BIST
signature result varies depending on the channel configuration.
OUTPUT TEST MODES
The output test options are shown in Table 22. When an output
test mode is enabled, the analog section of the ADC is discon-
nected from the digital back end blocks, and the test pattern is run
through the output formatting block. Some of the test patterns are
subject to output formatting, and some are not. The seed value for
the PN sequence tests can be forced by setting Bit 4 or Bit 5 of
the test mode register (Address 0x0D) to hold the generator in
reset mode. These tests can be performed with or without an
analog signal (if present, the analog signal is ignored), but they
do require an encode clock. For more information, see AN-877
Application Note, Interfacing to High Speed ADCs via SPI.