AD9983A/PCBZ Analog Devices Inc, AD9983A/PCBZ Datasheet
AD9983A/PCBZ
Specifications of AD9983A/PCBZ
Related parts for AD9983A/PCBZ
AD9983A/PCBZ Summary of contents
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FEATURES 8-bit analog-to-digital converters 140 MSPS maximum conversion rate Low PLL clock jitter at 140 MSPS Automatic gain matching Automated offset adjustment 2:1 input mux Power-down via dedicated pin or serial register 4:4:4, 4:2:2, and DDR output format modes Variable ...
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AD9983A TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Analog Interface Characteristics ................................................ 3 Absolute Maximum Ratings............................................................ 5 Explanation of Test Levels ........................................................... 5 Thermal ...
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SPECIFICATIONS ANALOG INTERFACE CHARACTERISTICS 1.8 V, DAV Table 1. Parameter RESOLUTION Number of bits LSB Size DC ACCURACY Differential Nonlinearity Integral Nonlinearity No Missing Codes ANALOG INPUT ...
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AD9983A Parameter POWER SUPPLY V Supply Voltage D V Supply Voltage DD PV Supply Voltage D DA Supply Voltage VDD V Supply Current ( Supply Current ( Supply Current (IPV ) D ...
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ABSOLUTE MAXIMUM RATINGS Table 2. Parameter DAV DD Analog Inputs REFHI REFLO Digital Inputs Digital Output Current Operating Temperature Storage Temperature Maximum Junction Temperature Maximum Case Temperature Stresses above those listed under Absolute Maximum ...
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AD9983A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V (1.8V AIN0 GND AIN1 V (1.8V AIN0 GND 7 SOGIN0 8 V (1.8V AIN1 GND 11 SOGIN1 12 ...
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Pin Type Pin Number Mnemonic Outputs RED [7: GREEN [7: BLUE [7:0] 25 DATACK 23 HSOUT 2 22 VSOUT 24 SOGOUT 21 O/E FIELD References 78 FILT 18 REFLO 20 REFHI ...
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AD9983A Table 5. Pin Function Descriptions Mnemonic Function R Analog Input for the Red AIN0 Channel 0 G Analog Input for the Green AIN0 Channel 0 B Analog Input for the Blue AIN0 Channel 0 R Analog Input for the ...
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Mnemonic Function REFLO, REFHI Input Amplifier Reference FILT External Filter Connection HSOUT Horizontal Sync Output VSOUT/A0 Vertical Sync Output Serial Port Address Input 0 SOGOUT Sync-On-Green Slicer Output O/E FIELD Odd/Even Field Bit for Interlaced Video SDA Serial Port Data ...
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AD9983A THEORY OF OPERATION The AD9983A is a fully integrated solution for capturing analog RGB or YPbPr signals and digitizing them for display on advanced TVs, flat panel monitors, projectors, and other types of digital displays. Implemented in a high ...
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In most PC graphics systems, black is transmitted between active video lines. With CRT displays, when the electron beam has completed writing a horizontal line on the screen (at the right side), the beam is deflected quickly to the left ...
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AD9983A Negative target codes are included in order to duplicate a fea- ture that is present with manual offset adjustment. The benefit that is being mimicked is the ability to easily adjust brightness on a display. By setting the target ...
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CLOCK GENERATION A PLL is used to generate the pixel clock. The Hsync input pro- vides a reference frequency to the PLL. A voltage controlled oscillator (VCO) generates a much higher pixel clock frequency. The pixel clock is divided by ...
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AD9983A The polarity of the coast signal may be set through the coast polarity register (Register 0x18, Bits[6:5]). Also, the polarity of the Hsync signal can be set through the Hsync polarity register (Register 0x12, Bits[5:4]). For both Hsync and ...
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AD9983A HSYNC0 ACTIVITY POLARITY DETECT DETECT HSYNC1 ACTIVITY POLARITY DETECT DETECT SYNC SLICER SOGIN0 ACTIVITY SYNC SLICER SOGIN1 ACTIVITY VSYNC0 ACTIVITY POLARITY DETECT DETECT VSYNC1 ACTIVITY POLARITY DETECT DETECT EXTCK/COAST SYNC PROCESSING The inputs of the sync processing section of ...
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AD9983A 700mV MAXIMUM +300mV SOG INPUT 0mV –300mV SOGOUT OUTPUT CONNECTED TO HSYNCIN COMPOSITE SYNC AT HSYNCIN VSYNCOUT FROM SYNC SEPARATOR Sync Separator As part of sync processing, the sync separator’s task is to extract Vsync from the composite sync ...
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HSYNCIN FILTER WINDOW HSYNCOUT VSYNC Vsync Filter and Odd/Even Fields The Vsync filter is used to eliminate spurious Vsyncs, maintain a stable timing relationship between the Vsync and Hsync output signals, and generate the odd/even field output. The filter works ...
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AD9983A POWER MANAGEMENT To meet display requirements for low standby power, the AD9983A includes a power-down mode. The power-down state can be controlled manually (via Pin 17 or Register 0x1E, Bit 3), or automatically by the chip. If automatic control ...
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DATAIN P0 HSYNCx DATACK DATAOUT HSOUT DATAIN P0 HSYNCx DATACK YOUT CB/CROUT HSOUT NOTES 1. PIXEL AFTER HSOUT CORRESONDS TO BLUE INPUT. 2. EVEN NUMBER OF PIXEL DELAY BETWEEN HSOUT AND DATAOUT. DATAIN P0 HSYNCx DATACK HSOUT DDR NOTES 1. ...
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AD9983A COAST TIMING In most computer systems, the Hsync signal is provided continuously on a dedicated wire. In these systems, the coast input and function are unnecessary and should not be used. In some systems, however, Hsync is disturbed during ...
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SERIAL CONTROL PORT A 2-wire serial interface control interface is provided two AD9983A devices may be connected to the 2-wire serial interface, with each device having a unique address. The 2-wire serial interface comprises a clock (SCL) ...
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AD9983A Serial Interface Read/Write Examples Write to One Control Register 1. Start signal Slave address byte (R/ W bit = low Base address byte 4. Data byte to base address 5. Stop signal Write to Four Consecutive Control ...
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SERIAL REGISTER MAP The AD9983A is initialized and controlled by a set of registers that determine the operating modes. An external controller is employed to write and read the control registers through the 2-wire serial interface port. Table 14. ...
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AD9983A Hex Read/Write, Default Address Read Only Bits Value 0x12 R/W 7 0*** **** 6 *0** **** 5 **0* **** 4 ***1 **** 3 **** 1*** 0x13 R/W 7:0 0010 0000 0x14 7 0*** **** R/W 6 *0** **** 5 ...
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Hex Read/Write, Default Address Read Only Bits Value 4 ***0 **** 3 **** 0*** 2 **** *0** 1 **** **0* 0 **** ***0 0x19 R/W 7:0 0000 1000 0x1A R/W 7:0 0010 0000 0x1B R/W 7 0*** **** 6 *1** ...
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AD9983A Hex Read/Write, Default Address Read Only Bits Value 3 **** 0*** 2 **** *0** 1 **** **0* 0 **** ***0 0x1F R/W 7:5 100* **** 4 ***1 **** 3 **** 0*** 2:1 **** *10* 0 **** ***0 0x20 7:6 ...
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Hex Read/Write, Default Address Read Only Bits Value 0x23 R/W 7:0 0000 1010 0x24 RO 7 _*** **** 6 *_** **** 5 **_* **** 4 ***_ **** 3 **** _*** 2 **** *_** 1 **** **_* 0 **** ***_ 0x25 ...
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AD9983A Hex Read/Write, Default Address Read Only Bits Value 0x2C R/W 7:5 000* **** 4 ***0 **** 3:0 **** 0000 0x2D R/W 7:0 1111 0000 0x2E R/W 7:0 1111 0000 0x34 2 **** *0** R/W 0x36 R/W 0 **** ***0 ...
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SERIAL CONTROL REGISTERS CHIP IDENTIFICATION 0x00—Bits[7:0] Chip Revision An 8-bit register that represents the silicon revision PLL DIVIDER CONTROL 0x01—Bits[7:0] PLL Divide Ratio MSBs The 8 MSBs of the 12-bit PLL divide ratio PLLDIV. The PLL derives a pixel ...
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AD9983A INPUT GAIN 0x05—Bits[6:0] Red Channel Gain Adjust The 7-Bit Red Channel Gain Control. The AD9983A can accommodate input signals with a full-scale range of between 0.5 V and 1.0 V p-p. Setting the red gain to 127 corresponds to ...
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Hsync Input Polarity Override This bit determines whether the chip selects the Hsync input polarity specified. Setting this bit to 0 allows the chip to automatically select the polarity of the input Hsync; setting it ...
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AD9983A 0x14—Bit[1] Vsync Duration Enable This enables the Vsync duration block, which is designed to be used with the Vsync filter. Setting the bit to 0 leaves the Vsync output duration unchanged. Setting the bit to 1 sets the Vsync ...
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Clamp Placement An 8-bit register that sets the position of the internally generated clamp. When EXTCLMP = 0 (Register 0x18, Bit 4), a clamp signal is generated internally position established by the clamp placement register (Register 0x19) ...
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AD9983A INPUT AND POWER CONTROL 0x1E—Bit[7] Channel Select Override This bit provides an override to the automatic input channel selection. Power-up default setting is 0. Table 43. Channel Source Override Override Result 0 Channel input source determined by chip 1 ...
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OUTPUT CONTROL 0x1F—Bits[7:5] Output Mode These bits choose between three options for the output mode. In 4:4:4 mode, RGB is standard. In 4:2:2 mode, YCbCr is standard, which allows a reduction in the number of output pins from 24 to ...
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AD9983A SYNC PROCESSING 0x20—Bit[2] PLL Sync Filter This bit selects which signal the PLL uses. It can select between either raw Hsync or SOG or filtered versions. The filtering of the Hsync and SOG can eliminate nearly all extraneous transitions, ...
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SOGIN1 Detection Bit This bit is used to indicate when activity is detected on the SOGIN1 input pin. If SOG is held high or low, activity is not detected. The sync processing block diagram shows where this function is ...
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AD9983A 0x2C—Bits[7:5] Auto-Offset Hold Must be written to 0x00 for proper operation. 0x2C—Bit[4] Auto-Offset Hold A bit for controlling whether the auto-offset function runs continuously or runs once and holds the result. Continuous updates are recommended because this allows the ...
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PCB LAYOUT RECOMMENDATIONS The AD9983A is a high precision, high speed analog device. To achieve the maximum performance from the part important to have a well laid-out board. The Analog Interface Inputs section provides a guide for designing ...
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AD9983A OUTPUTS (BOTH DATA AND CLOCKS) Try to minimize the trace length that the digital outputs have to drive. Longer traces have higher capacitance and require more instantaneous current to drive, which creates more internal digital noise. Shorter traces reduce ...
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OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range 1 AD9983AKSTZ-140 0°C to 70°C AD9983A/PCB RoHS Compliant Part. 16.20 16.00 SQ 0.75 1.60 15.80 0.60 MAX 0.45 ...
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AD9983A NOTES Rev Page ...
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NOTES Rev Page AD9983A ...
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AD9983A NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06475-0-5/07(0) Rev Page ...