AD9983A/PCBZ Analog Devices Inc, AD9983A/PCBZ Datasheet - Page 24

• Manufacturer Part Number: AD9983A/PCBZ
• Description: Pb-free EVALUATION Kit AD9983A
• Manufacturer: Analog Devices Inc
• Series: Advantiv®r

Specifications of AD9983A/PCBZ

• Main Purpose: Video, Video Processing
• Embedded: No
• Utilized Ic / Part: AD9983A
• Primary Attributes: 3 x 8-Bit 140 MSPS ADC's
• Secondary Attributes: Integrated PLL & VCO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9983A
Hex
Address
0x12
0x13
0x14
0x15
0x16
0x17
0x18
Read/Write,
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits
7
6
5
4
3
7:0
7
6
5
4
3
2
1
7:0
7:0
7:0
7
6
5
Default
Value
0*** ****
*0** ****
**0* ****
***1 ****
**** 1***
0010 0000
0*** ****
*0** ****
**0* ****
***1 ****
**** 1***
**** *0**
**** **0*
0000 1010
0000 0000
0000 0000
0*** ****
*0** ****
**1* ****
Register Name
Hsync Control
Hsync Duration
Vsync Control
Vsync Duration
Precoast
Postcoast
Coast and Clamp
Control
Rev. 0 | Page 24 of 44
Description
Active Hsync Override.
0 = The chip determines the active Hsync source
1 = The active Hsync source is set by Reg. 0x12, Bit 6
Selects the source of the Hsync for PLL and sync processing. This bit is
used only if Reg. 0x12, Bit 7 is set to 1 or if both syncs are active.
0 = Hsync is from HSYNCx input pin
1 = Hsync is from SOGINx
Hsync Input Polarity Override.
0 = The chip selects the Hsync input polarity
1 = The polarity of the input Hsync is controlled by Reg. 0x12, Bit 4
This applies to both HSYNC0 and HSYNC1.
Hsync Input Polarity. This bit is used only if Reg. 0x12, Bit 5 is set to 1.
0 = Active low input Hsync
1 = Active high input Hsync
Sets the polarity of the Hsync output signal.
0 = Active low Hsync output
1 = Active high Hsync output
Sets the number of pixel clocks that HSOUT is active.
Active Vsync Override.
0 = The chip determines the active Vsync source
1 = The active Vsync source is set by Reg. 0x14, Bit 6
Selects the source of Vsync for the sync processing. This bit is used
only if Reg. 0x14, Bit 7 is set to 1.
0 = Vsync is from the Vsync input pin
1 = Vsync is from the sync separator
Vsync Input Polarity Override. This applies to both VSYNC0 and
VSYNC1.
0 = The chip selects the input Vsync polarity
1 = The polarity of the input Vsync is set by Reg. 0x14, Bit 4
Vsync Input Polarity. This bit is used only if Reg. 0x14, Bit 5 is set to 1.
0 = Active low input Vsync
1 = Active high input Vsync
Sets the polarity of the output Vsync signal.
0 = Active low output Vsync
1 = Active high output Vsync
Vsync Filter Enable. This needs to be enabled when using the
Hsync to Vsync counter.
0 = The Vsync filter is disabled
1 = The Vsync filter is enabled
Enables the Vsync duration block. This is designed to be used with
the Vsync filter.
0 = Vsync output duration is unchanged
1 = Vsync output duration is set by Reg. 0x15
Sets the number of Hsyncs that Vsync out is active. This is only
used if Reg. 0x14, Bit 1 is set to 1.
The number of Hsync periods to coast prior to Vsync.
The number of Hsync periods to coast after Vsync.
Coast Source. Selects the source of the coast signal.
0 = Using internal coast generated from Vsync
1 = Using external coast signal from external COAST pin
Coast Polarity Override.
0 = The chip selects the external coast polarity
1 = The polarity of the external coast signal is set by Reg. 0x18, Bit 5
Coast Input Polarity. This bit is used only if Reg. 0x18, Bit 6 is set to 1.
0 = Active low external coast
1 = Active high external coast