ADP5588-EVALZ Analog Devices Inc, ADP5588-EVALZ Datasheet - Page 18

• Manufacturer Part Number: ADP5588-EVALZ
• Description: Column Keypad Scanner & GPIO Port Expand
• Manufacturer: Analog Devices Inc

Specifications of ADP5588-EVALZ

• Main Purpose: Interface, GPIO Expander
• Embedded: No
• Utilized Ic / Part: ADP5588
• Primary Attributes: 8-Bit 18-Port GPIO Expander
• Secondary Attributes: I²C Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADP5588
Register Name
KEY_EVENTI
(Register 0x0C)
KEY_EVENTJ
(Register 0x0D)
1
2
Table 23. KP_LCK_TMR—Register 0x0E (Keypad Unlock 1 to Keypad Unlock 2 Timer)
Register Name
KP_LCK_TMR
(Register 0x0E)
1
2
Table 24. UNLOCK1—Register 0x0F (Unlock Key 1)
Register Name
UNLOCK1
(Register 0x0F)
Table 25. UNLOCK2—Register 0x10 (Unlock Key 2)
Register Name
UNLOCK2
(Register 0x10)
Table 26. GPIO_INT_STATx—Register 0x11 to Register 0x13 (GPIO Interrupt Status)
Register Name
GPIO_INT_STAT1
(Register 0x11)
GPIO_INT_STAT2
(Register 0x12)
GPIO_INT_STAT3
Table 27. GPIO_DAT_STATx—Register 0x14 to Register 0x16 (GPIO Data Status)
Register Name
GPIO_DAT_STAT1
(Register 0x14)
GPIO_DAT_STAT2
(Register 0x15)
GPIO_DAT_STAT3
(Register 0x16)
(Register 0x13)
Data in key events is provided as a FIFO, where data is sequentially provided on each read, regardless of an event register read. The user can read register Event A only
for an event count or can read registers sequentially.
KE[6:0] reflects the value 1 to 80 for key press events and the value 97 to 114 for GPI events. For KE[7:0], 0 = key released event, 1 = key pressed event. For GPIEM_CFG,
0 reflects a change in the GPI from GPI_INT_LVL = true to GPI_INT_LVL = false; 1 reflects a change in the GPI in which the GPI_INT_LVL condition becomes true.
When the keypad lock interrupt mask timer is enabled, the user must press two specific keys before a keylock interrupt is generated or keypad events are recorded.
After the keypad is locked, the first time that the user presses any key, a key event interrupt is generated. No additional interrupt is generated unless both unlock key
sequences are correct; then a keylock interrupt is generated. When the interrupt mask timer is disabled (0), an interrupt is generated only when the correct full unlock
sequence is completed.
The Unlock 1 and Unlock 2 timer keys can be either a key sequence or GPIEM_CFG sequence. The unlock timer keys can be programmed with any value of the keys in
the keypad matrix or any GPI values that are part of the key event table. The keylock enable bit (Bit 6, Register 0x03) must be set to lock the keypad.
Register Description
Keypad UnLock 1 to Keypad UnLock 2 timer[2:0]
(0: disabled, 1 sec to 7 sec)
Keypad Lock Interrupt Mask Timer[7:3]
(0: disabled, 0 sec to 31 sec)
Register Description
Unlock Key 1[6:0] (contains key number
for Unlock Key 1; 0: disabled)
Register Description
Unlock Key 2[6:0] (contains key number
for Unlock Key 2; 0: disabled)
Register Description
GPIO interrupt status (used to check
GPIO interrupt status, cleared on read)
GPIO interrupt status (used to check
GPIO interrupt status, cleared on read)
GPIO interrupt status (used to check
GPIO interrupt status, cleared on read)
Register Description
GPIO data status (shows GPIO state
when read for inputs and outputs)
GPIO data status (shows GPIO state
when read for inputs and outputs)
GPIO data status (shows GPIO state
when read for inputs and outputs)
Register Description
Key Event Register B status (KE[6:0] = Key number),
KP[7] = 0: released, 1: pressed (cleared on read)
Key Event Register B status (KE[6:0] = Key number),
KP[7] = 0: released, 1: pressed (cleared on read)
1, 2
Rev. B | Page 18 of 28
Bit 7
N/A
Bit 7
N/A
Bit 7
R7IS
C7IS
N/A
Bit 7
R7DS
C7DS
N/A
Bit 7
KIMT7
Bit 7
KI7
KJ7
Bit 6
ULK6
Bit 6
ULK6
Bit 6
R6IS
C6IS
N/A
Bit 6
R6DS
C6DS
N/A
Bit 6
KIMT6
Bit 6
KI6
KJ6
Bit 5
ULK5
Bit 5
ULK5
Bit 5
R5IS
C5IS
N/A
Bit 5
R5DS
C5DS
N/A
Bit 5
KIMT5
Bit 5
KI5
KJ5
Bit 4
ULK4
Bit 4
ULK4
Bit 4
R4IS
C4IS
N/A
Bit 4
R4DS
C4DS
N/A
Bit 4
KIMT4
Bit 4
KI4
KJ4
Bit 3
ULK3
Bit 3
ULK3
Bit 3
R3IS
C3IS
N/A
Bit 3
R3DS
C3DS
N/A
Bit 3
KIMT3
Bit 3
KI3
KJ3
Bit 2
Bit 2
Bit 2
Bit 2
ULK2
ULK2
R2IS
C2IS
N/A
R2DS
C2DS
N/A
Bit 2
KLLT2
Bit 2
KI2
KJ2
Bit 1
Bit 1
Bit 1
R1IS
Bit 1
R1DS
C1DS
ULK1
ULK1
C1IS
C9IS
C9DS
Bit 1
KLLT1
Bit 1
KI1
KJ1
Bit 0
ULK0
Bit 0
ULK0
Bit 0
R0IS
C0IS
C8IS
Bit 0
R0DS
C0DS
C8DS
Bit 0
KI0
KJ0
Bit 0
KLLT0