ADP5588-EVALZ Analog Devices Inc, ADP5588-EVALZ Datasheet - Page 20

• Manufacturer Part Number: ADP5588-EVALZ
• Description: Column Keypad Scanner & GPIO Port Expand
• Manufacturer: Analog Devices Inc

Specifications of ADP5588-EVALZ

• Main Purpose: Interface, GPIO Expander
• Embedded: No
• Utilized Ic / Part: ADP5588
• Primary Attributes: 8-Bit 18-Port GPIO Expander
• Secondary Attributes: I²C Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADP5588
Table 32. GPIO_DIRx—Register 0x23 to Register 0x25 (GPIO Data Direction)
Register Name
GPIO_DIR1
(Register 0x23)
GPIO_DIR2
(Register 0x24)
GPIO_DIR3
(Register 0x25)
Table 33. GPIO_INT_LVLx—Register 0x26 to Register 0x28 (GPIO Edge/Level Detect)
Register Name
GPIO_INT_LVL1
(Register 0x26)
GPIO_INT_LVL2
(Register 0x27)
GPIO_INT_LVL3
(Register 0x28)
Table 34. DEBOUNCE_DISx—Register 0x29 to Register 0x2B (Debounce Disable)
Register Name
DEBOUNCE_DIS1
(Register 0x29)
DEBOUNCE_DIS2
(Register 0x2A)
DEBOUNCE_DIS3
(Register 0x2B)
Table 35. GPIO_PULLx—Register 0x2C to Register 0x2E (GPIO Pull Disable)
Register Name
GPIO_PULL1
(Register 0x2C)
GPIO_PULL2
(Register 0x2D)
GPIO_PULL3
(Register 0x2E)
Table 36. Register 0x2F
Field
Not Used
Register Description
GPIO pull disable (remove pull-ups from inputs)
0: Pull enabled
1: Pull disabled
GPIO pull disable (remove pull-ups from inputs)
0: Pull enabled
1: Pull disabled
GPIO pull disable (remove pull-ups from inputs)
0: Pull enabled
1: Pull disabled
Register Description
GPIO data direction
0: GPIO
1: Output
GPIO data direction
0: GPIO
1: Output
GPIO data direction
0: GPIO
1: Output
Register Description
GPIO INT level detect
0: Low
1: High
GPIO INT level detect
0: Low
1: High
GPIO INT level detect
0: Low
1: High
Register Description
Debounce disable (inputs)
0: Enabled
1: Disabled
Debounce disable (inputs)
0: Enabled
1: Disabled
Debounce disable (inputs)
0: Enabled
1: Disabled
Bit
N/A
Rev. B | Page 20 of 28
Bit 7
Bit 7
R7IL
C7IL
N/A
Bit 7
R7D
C7D
N/A
R7DD
C7DD
N/A
Bit 7
R7PD
C7PD
N/A
Bit 6
R6D
C6D
N/A
Bit 6
R6IL
C6IL
N/A
Bit 6
R6DD
C6DD
N/A
Bit 6
R6PD
C6PD
N/A
Bit 5
R5D
C5D
N/A
Bit 5
R5IL
C5IL
N/A
Bit 5
R5DD
C5DD
N/A
Description
Not used
Bit 5
R5PD
C5PD
N/A
Bit 4
Bit 4
R4D
C4D
N/A
R4IL
C4IL
N/A
Bit 4
R4DD
C4DD
N/A
Bit 4
R4PD
C4PD
N/A
Bit 3
Bit 3
R3D
C3D
N/A
R3IL
C3IL
N/A
Bit 3
R3DD
C3DD
N/A
Bit 3
R3PD
C3PD
N/A
Bit 2
Bit 2
Bit 2
R2D
C2D
N/A
R2IL
C2IL
N/A
R2DD
C2DD
N/A
Bit 2
R2PD
C2PD
N/A
Bit 1
Bit 1
C1IL
C9IL
Bit 1
R1D
C1D
C9D
R1IL
R1DD
C1DD
C9DD
Bit 1
R1PD
C1PD
C9PD
Bit 0
Bit 0
R0IL
C0IL
C8IL
Bit 0
R0DD
C0DD
C8DD
R0D
C0D
C8D
Bit 0
R0PD
C0PD
C8PD