ADSP-21062LKS-133 Analog Devices Inc, ADSP-21062LKS-133 Datasheet - Page 17

• Manufacturer Part Number: ADSP-21062LKS-133
• Description: Digital Signal Processor(DSP) IC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21062LKS-133

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 33MHz
• Non-volatile Memory: External
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 240-MQFP, 240-PQFP
• Device Core Size: 32b
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 33MHz
• Mips: 33
• Device Input Clock Speed: 33MHz
• Ram Size: 256KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: MQFP
• Lead Free Status / Rohs Status: Not Compliant

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
EXTERNAL POWER DISSIPATION (5 V)
Total power dissipation has two components, one due to inter-
nal circuitry and one due to the switching of external output
drivers. Internal power dissipation is dependent on the instruc-
tion execution sequence and the data operands involved.
Internal power dissipation is calculated in the following way:
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
and is calculated by:
The load capacitance should include the processor’s package
capacitance (CIN). The switching frequency includes driving
the load high and then back low. Address and data pins can
Table 5. External Power Calculations (5 V Devices)
Pin Type
Address
MS0
WR
Data
ADDRCLK
• the number of output pins that switch during each cycle
• the maximum frequency at which they can switch (f)
• their load capacitance (C)
• their voltage swing (V
P
P
INT
(O)
EXT
= I
= O u C u V
DDIN
u V
DD
DD
2
u f
No. of Pins
15
1
1
32
1
DD
)
% Switching
50
0
–
50
–
Rev. F | Page 17 of 64 | March 2008
u C
u 44.7 pF
u 44.7 pF
u 44.7 pF
u 14.7 pF
u 4.7 pF
drive high and low at a maximum rate of 1/(2t
strobe can switch every cycle at a frequency of 1/t
switch at 1/(2t
Example: Estimate P
The P
drive:
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
Note that the conditions causing a worst-case P
from those causing a worst-case P
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching
simultaneously.
• A system with one bank of external data memory RAM
• Four 128K u 8 RAM chips are used, each with a load of
• External data memory writes occur every other cycle, a rate
• The instruction cycle rate is 40 MHz (t
P
(32-bit)
10 pF
of 1/(4t
TOTAL
EXT
u f
u 10 MHz
u 10 MHz
u 20 MHz
u 10 MHz
u 20 MHz
equation is calculated for each class of pins that can
= P
CK
EXT
), with 50% of the pins switching
CK
), but selects can switch on each cycle.
+ (I
DDIN
EXT
2
with the following assumptions:
u 5.0 V)
u V
u 25 V
u 25 V
u 25 V
u 25 V
u 25 V
DD
2
INT
. Maximum P
= P
= 0.084 W
= 0.000 W
= 0.022 W
= 0.059 W
= 0.002 W
CK
= 25 ns)
EXT
CK
EXT
). The write
P
CK
INT
EXT
are different
. Select pins
cannot
= 0.167 W