ADSP-21369KSWZ-1A Analog Devices Inc, ADSP-21369KSWZ-1A Datasheet - Page 28

• Manufacturer Part Number: ADSP-21369KSWZ-1A
• Description: 266 MHz, Shared Memory,S/PDIF EPAD PBfr
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21369KSWZ-1A

• Interface: DAI, DPI
• Clock Rate: 266MHz
• Non-volatile Memory: ROM (768 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-LQFP
• Device Core Size: 32/40Bit
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 266MHz
• Mips: 266
• Device Input Clock Speed: 266MHz
• Ram Size: 256KB
• Program Memory Size: 768KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: LQFP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-21369-EZLITE - KIT EVAL EZ LITE ADDS-21369
• Lead Free Status / Rohs Status: Compliant

ADSP-21367/ADSP-21368/ADSP-21369
SDRAM Interface Timing (166 MHz SDCLK)
The 166 MHz access speed is for a single processor. When mul-
tiple ADSP-21368 processors are connected in a shared memory
system, the access speed is 100 MHz.
Table 22. SDRAM Interface Timing
1
2
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
The processor needs to be programmed in t
Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDCKE.
SSDAT
HSDAT
SDCLK
SDCLKH
SDCLKL
DCAD
HCAD
DSDAT
ENSDAT
DATA Setup Before SDCLK
DATA Hold After SDCLK
SDCLK Period
SDCLK Width High
SDCLK Width Low
Command, ADDR, Data Delay After SDCLK
Command, ADDR, Data Hold After SDCLK
Data Disable After SDCLK
Data Enable After SDCLK
CMND ADDR
DATA (OUT)
DATA (IN)
SDCLK
(OUT)
SDCLK
1
= 2.5 t
CCLK
t
SSDAT
mode when operated at 350MHz, 366MHz and 400MHz.
Rev. E | Page 28 of 60 | July 2009
2
Figure 17. SDRAM Interface Timing
2
t
DCAD
t
SDCLK
Min
500
1.23
6.83
3
3
1.2
1.3
t
t
HSDAT
ENSDAT
366 MHz
Max
4.8
5.3
t
t
DCAD
HCAD
t
SDCLKL
Min
500
1.23
7.14
3
3
1.2
1.3
t
HCAD
t
350 MHz
SDCLKH
t
DSDAT
Max
4.8
5.3
Min
500
1.23
6.0
2.6
2.6
1.2
1.3
All Other Speed
Grades
Max
4.8
5.3
Unit
ps
ns
ns
ns
ns
ns
ns
ns
ns