ADSP-21992BSTZ Analog Devices Inc, ADSP-21992BSTZ Datasheet
ADSP-21992BSTZ
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ADSP-21992BSTZ Summary of contents
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... FEATURES ADSP-2199x, 16-bit, fixed-point DSP core with up to 160 MIPS sustained performance 48K words of on-chip RAM, as 32K words on-chip 24-bit pro- gram RAM, and 16K words on-chip, 16-bit data RAM External memory interface Dedicated memory DMA controller for data/instruction transfer between internal/external memory ...
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... ADSP-21992 TABLE OF CONTENTS General Description ................................................. 3 DSP Core Architecture ........................................... 3 Memory Architecture ............................................ 5 Bus Request and Bus Grant ..................................... 6 DMA Controller ................................................... 7 DSP Peripherals Architecture .................................. 7 Serial Peripheral Interface (SPI) Port ......................... 7 DSP Serial Port (SPORT) ........................................ 8 Controller Area Network (CAN) Module ................... 9 Analog-to-Digital Conversion System ........................ 9 Voltage Reference ................................................. 9 PWM Generation Unit ......................................... 10 Auxiliary PWM Generation Unit ...
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... RAM, and 16K words (16-bit) of data RAM. Fabricated in a high speed, low power, CMOS process, the ADSP-21992 operates with a 6.25 ns instruction cycle time for a 160 MHz CCLK, with a 6.67 ns instruction cycle time for a 150 MHz CCLK, and with a 10.0 ns instruction cycle time for a 100 MHz CCLK ...
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... A powerful program sequencer controls the flow of instruction execution. The sequencer supports conditional jumps, subrou- tine calls, and low interrupt overhead. With internal loop counters and loop stacks, the ADSP-21992 executes looped code with zero overhead; no explicit jump instructions are required to maintain loops. ...
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... Program memory can store both instructions and data, permit- ting the ADSP-21992 to fetch two operands in a single cycle, one from program memory and one from data memory. The DSP dual memory buses also let the embedded SHARC core fetch an operand from data memory and the next instruction from pro- gram memory in a single cycle ...
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... ROM is located on Page 255 in the DSP memory space map, starting at address 0xFF0000. External (Off-Chip) Memory Each of the off-chip memory spaces of the ADSP-21992 has a separate control register, so applications can configure unique access parameters for each space. The access parameters include read and write wait counts, wait state completion mode, I/O clock divide ratio, write hold time extension, strobe polarity, and data bus width ...
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... The bus request feature operates at all times, even while the DSP is booting and RESET is active. The ADSP-21992 asserts the BGH pin when it is ready to start another external port access, but is held off because the bus was previously granted. This mechanism can be extended to define more complex arbitration protocols for implementing more elaborate multimaster systems ...
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... SPISEL7) that are multiplexed with the PF1 to PF7 flag I/O lines. The SPISS input is used to select the ADSP-21992 as a slave to an external master. The SPISEL1 to SPISEL7 outputs can be used by the ADSP-21992 (acting as a master) to select/enable up to seven external slaves in a multidevice SPI configuration ...
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... At the 20 MHz sampling rate, the first data value is valid approximately 375 ns after the convert start command. All eight channels are converted in approximately 725 ns. The core of the ADSP-21992 provides 14-bit data such that the stored data values in the ADC data registers are 14 bits wide. VOLTAGE REFERENCE The ADSP-21992 contains an on-board band gap reference that can be used to provide a precise 1 ...
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... Separate auxiliary PWM synchronization signal and associ- ated interrupt (can be used to trigger ADC convert start). • Separate auxiliary PWM shutdown signal (AUXTRIP). The ADSP-21992 integrates a 2-channel, 16-bit, auxiliary PWM output unit that can be programmed with variable frequency, variable duty cycle values and may operate in two different modes, independent mode or offset mode ...
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... EIUSTAT register is set, and an EIU count error interrupt is generated. The encoder interface unit of the ADSP-21992 contains a 16-bit loop timer that consists of a timer register, period register, and scale register so that it can be programmed to time out and reload at appropriate intervals ...
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... This scheme permits the user to assign the number of specific interrupts that are unique to their application to the interrupt scheme of the ADSP-2199x core. The user can then use the existing interrupt priority control scheme to dynamically con- trol the priorities of the 12 core interrupts. ...
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... Power-down core • Power-down core/peripherals • Power-down all Idle Mode When the ADSP-21992 is in idle mode, the DSP core stops exe- cuting instructions, retains the contents of the instruction pipeline, and waits for an interrupt. The core clock and periph- eral clock continue running. ...
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... BMODE2, BMODE1, and BMODE0 pins. The dedicated BMODE2, BMODE1, and BMODE0 pins are sampled at hardware reset. The particular boot mode for the ADSP-21992 associated with the settings of the BMODE2, BMODE1, BMODE0 pins is ) power supplies. The defined in ...
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... INSTRUCTION SET DESCRIPTION The ADSP-21992 assembly language instruction set has an alge- braic syntax that was designed for ease of coding and readability. The assembly language, which takes full advantage of the unique architecture of the processor, offers the following benefits: • SHARC assembly language syntax is a superset of and ...
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... Analog Devices DSP emulators use the IEEE 1149.1 JTAG test access port of the ADSP-21992 processor to monitor and con- trol the target board processor during emulation. The emulator provides full speed emulation, allowing inspection and modifi- cation of memory, registers, and processor stacks ...
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... PIN FUNCTION DESCRIPTIONS ADSP-21992 pin definitions are listed in ADSP-21992 inputs are asynchronous and can be asserted asyn- chronously to CLKIN (or to TCK for TRST). Unused inputs should be tied or pulled to V except for ADDR21–0, DATA15–0, PF7–0, and inputs that have internal pull-up or pull-down resistors (TRST, BMODE0, BMODE1, BMODE2, BYPASS, TCK, TMS, TDI, PWMPOL, PWMSR, and RESET)— ...
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... ADSP-21992 Table 4. Pin Descriptions (Continued) Name Type BSHAN A, I CAPT A, O CAPB A, O VREF SENSE A, I CML A, O CONVST D, I CANRX D, I CANTX D, OT PF15 D, BT, PD PF14 D, BT, PD PF13 D, BT, PD PF12 D, BT, PD PF11 D, BT, PD PF10 D, BT, PD PF9 D, BT, PD PF8 D, BT, PD PF7/SPISEL7 ...
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... PWMPOL PWMTRIP PWMSR AVDD (2 pins AVSS (2 pins VDDINT (6 pins VDDEXT (10 pins GND (16 pins Function PWM Synchronization PWM Polarity PWM Trip PWM SR Mode Select Analog Supply Voltage Analog Ground Digital Internal Supply Digital External Supply Digital Ground Rev Page August 2007 ADSP-21992 ...
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... The HCLK frequency may be made to appear at the dedicated CLKOUT pin of the device. For low power operation, however, the CLKOUT pin can be disabled. 2 The peripherals operate at the HCLK rate, which may be selected to be equal to CCLK or CCLK maximum MHz HCLK for the ADSP-21992BBC order to attain the correct CCLK and HCLK values, the input clock frequency or crystal frequency depends on the internal operation of the clock generation PLL circuit and the associated frequency ratio ...
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... The HCLK frequency may be made to appear at the dedicated CLKOUT pin of the device. For low power operation, however, the CLKOUT pin can be disabled. 2 The peripherals operate at the HCLK rate, which may be selected to be equal to CCLK or CCLK maximum MHz HCLK for the ADSP-21992YST order to attain the correct CCLK and HCLK values, the input clock frequency or crystal frequency depends on the internal operation of the clock generation PLL circuit and the associated frequency ratio ...
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... The I supply currents are affected by the operating frequency of the device. The guaranteed numbers are based on an assumed CCLK = 150 MHz, HCLK = 75 MHz DD for the ADSP-21992BBC. I refers only to the current consumption on the internal power supply lines (V DD power supply is very much dependent on the particular connection of the device in the final system. ...
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... ELECTRICAL CHARACTERISTICS Table 10. Electrical Characteristics—ADSP-21992YBC Parameter Conditions V High Level Input Voltage IH V High Level Input Voltage IH V High Level Input Voltage IL V High Level Output Voltage OH V Low Level Output Voltage OL I High Level Input Current IH I High Level Input Current ...
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... The I supply currents are affected by the operating frequency of the device. The guaranteed numbers are based on an assumed CCLK = 160 MHz, HCLK = 80 MHz DD for the ADSP-21992BST. I refers only to the current consumption on the internal power supply lines (V DD power supply is very much dependent on the particular connection of the device in the final system. ...
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... Table 12. Electrical Characteristics—ADSP-21992YST Parameter Conditions V High Level Input Voltage IH V High Level Input Voltage IH V High Level Input Voltage IL V High Level Output Voltage OH V Low Level Output Voltage OL I High Level Input Current IH I High Level Input Current IH I High Level Input Current ...
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... ADSP-21992 Table 13. Peripherals Electrical Characteristics—ADSP-21992BBC Parameter Description ANALOG-TO-DIGITAL CONVERTER AC Specifications SNR Signal-to-Noise Ratio SNRD Signal-to-Noise and Distortion THD Total Harmonic Distortion CTLK Channel-Channel Crosstalk CMRR Common-Mode Rejection Ratio PSRR Power Supply Rejection Ratio Accuracy INL Integral Nonlinearity DNL Differential Nonlinearity ...
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... Table 14. Peripherals Electrical Characteristics—ADSP-21992BST Parameter Description ANALOG-TO-DIGITAL CONVERTER AC Specifications SNR Signal-to-Noise Ratio SNRD Signal-to-Noise and Distortion THD Total Harmonic Distortion CTLK Channel-Channel Crosstalk CMRR Common-Mode Rejection Ratio PSRR Power Supply Rejection Ratio Accuracy INL Integral Nonlinearity DNL Differential Nonlinearity No Missing Codes ...
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... ADSP-21992 Table 15. Peripherals Electrical Characteristics—ADSP-21992YBC Parameter Description ANALOG-TO-DIGITAL CONVERTER AC Specifications SNR Signal-to-Noise Ratio SNRD Signal-to-Noise and Distortion THD Total Harmonic Distortion CTLK Channel-Channel Crosstalk CMRR Common-Mode Rejection Ratio PSRR Power Supply Rejection Ratio Accuracy INL Integral Nonlinearity DNL Differential Nonlinearity ...
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... Table 16. Peripherals Electrical Characteristics—ADSP-21992YST Parameter Description ANALOG-TO-DIGITAL CONVERTER AC Specifications SNR Signal-to-Noise Ratio SNRD Signal-to-Noise and Distortion THD Total Harmonic Distortion CTLK Channel-Channel Crosstalk CMRR Common-Mode Rejection Ratio PSRR Power Supply Rejection Ratio Accuracy INL Integral Nonlinearity DNL Differential Nonlinearity No Missing Codes ...
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... ADSP-21992 ABSOLUTE MAXIMUM RATINGS Parameter 1 Internal (Core) Supply Voltage (V ) DDINT 1 External (I/O) Supply Voltage (V ) DDEXT 2 Input Voltage1, (V – Output Voltage Swing (V – Load Capacitance1 ( Core Clock Period1 (t ) CCLK Core Clock Frequency1 (f ) CCLK Peripheral Clock Period1 (t ) HCLK Peripheral Clock Frequency1 (f ) HCLK Storage Temperature Range1 (T ...
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... MHz/80 MHz for the ADSP-21992BST, 150 MHz/75 MHz for both the ADSP-21992BBC and ADSP-21992YBC, and 100 MHz/50 MHz for the ADSP-21992YST, when the peripheral clock rate is one- Table 17. Clock In and Clock Out Cycle Timing Parameter Timing Requirements ...
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... ADSP-21992 t CK CLKIN t t CKL CKH RESET MSEL6–0 BYPASS DF CLKOUT t WRST t MSD PFD MSS MSH t CKOD Figure 7. Clock In and Clock Out Cycle Timing Rev Page August 2007 t CKO ...
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... Flag Input Hold Is Asynchronous HFI Switching Characteristics t Flag Output Delay with Respect to CLKOUT DFO t Flag Output Hold After CLKOUT High HFO CLKOUT PF (OUTPUT) PF (INPUT DFO HFO FLAG OUTPUT t HFI FLAG INPUT Figure 8. Programmable Flags Cycle Timing Rev Page August 2007 ADSP-21992 Min Max Unit ...
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... ADSP-21992 Timer PWM_OUT Cycle Timing Table 19 and Figure 9 describe timer expired operations. The input signal is asynchronous in “width capture mode” and has an absolute maximum input frequency of 40 MHz. Table 19. Timer PWM_OUT Cycle Timing Parameter Switching Characteristic t Timer Pulse Width Output HTO ...
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... EMI clock. ACK low causes the DSP to wait, and the DSP requires two EMI clock cycles after ACK goes high to finish the access. For more information, see the External Port chapter in the ADSP-2199x DSP Hardware Reference. Min 12.5 ...
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... ADSP-21992 MS3–0 IOMS BMS A21–0 WR ACK D15– CSWS AWS t AKW t t CDA DSW t DWSAK Figure 10. External Port Write Cycle Timing Rev Page August 2007 t WSCS t WSA t WWR t CDD t DHW ...
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... These are timing parameters that are based on worst-case operating conditions (number of wait states specified in wait register) Min 0.5t 0.5t 0. the peripheral clock period. HCLK t . EMICLK Rev Page August 2007 ADSP-21992 Max HCLK 3 t – 5+W EMICLK EMICLK EMICLK 0.5t – 1 EMICLK – 3 EMICLK – ...
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... ADSP-21992 MS3–0 IOMS BMS A21–0 RD ACK D15– CSRS ARS t DRSAK t AKW t CDA t RDA t ADA t SDA Figure 11. External Port Read Cycle Timing Rev Page August 2007 t RSCS t RSA t RWR ...
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... CLKOUT High to BG Deasserted Hold Time EBG t CLKOUT High to BGH Asserted Setup DBH t CLKOUT High to BGH Deasserted Hold Time EBH the peripheral clock period. HCLK 2 These are timing parameters that are based on worst-case operating conditions. Min 4 Rev Page August 2007 ADSP-21992 Max Unit HCLK ...
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... ADSP-21992 CLKOUT MS3–0 IOMS BMS A21– BGH DBG t DBH Figure 12. External Port Bus Request and Grant Cycle Timing Rev Page August 2007 EBG t EBH ...
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... If external RFSD/TFS setup to RCLK/TCLK > 0.5t describe SPORT RFS Setup Before RCLK and t . DDTLFSE , t and t apply; otherwise, t LSCK DDTLSCK DTENLSCK Rev Page August 2007 ADSP-21992 Min Max 4 4 1.5 4 0.5t –1 HCLK 2t HCLK 13.4 4 13.4 4 0.5t – 3.5 0.5t + 2.5 HCLK HCLK 0 12 ...
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... ADSP-21992 DATA RECEIVE-INTERNAL CLOCK DRIVE EDGE t SCLKIW RCLK t DFSE t HOFSE t SFSI RFS t SDRI DR NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT-INTERNAL CLOCK DRIVE EDGE t SCLKIW TCLK t DFSE t HOFSE t SFSI TFS t DDTI t HDTI DT NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE ...
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... LATE EXTERNAL TFS DRIVE SAMPLE TCLK t SFSE / I TFS t DTENLFSE 1ST BIT DT t DDTLFSE Figure 14. Serial Port—External Late Frame Sync (Frame Sync Setup > 0.5t Rev Page August 2007 DRIVE t HOSFSE DDTE HDTE/ I 2ND BIT DRIVE t HOSFSE DDTE / I t HDTE/ I 2ND BIT ) SCLK ADSP-21992 ...
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... ADSP-21992 EXTERNAL RFS WITH MCE = 1, MFD = 0 RCLK RFS DT LATE EXTERNAL TFS TCLK TFS DT Figure 15. Serial Port—External Late Frame Sync (Frame Sync Setup < 0.5t DRIVE SAMPLE DRIVE t t SFSE/ I HOFSE DDTE / I DTENLFSE t HDTE/ I 1ST BIT t DDTLFSE DRIVE SAMPLE DRIVE t t HOFSE/ I ...
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... Sequential Transfer Delay SPITDM t SCLK Edge to Data Output Valid (Data Out Delay) DDSPID t SCLK Edge to Data Output Invalid (Data Out Hold) HDSPID Min Rev Page August 2007 ADSP-21992 Max Unit ns ns –3 ns HCLK –3 ns HCLK –3 ns HCLK –1 ns HCLK –3 ns HCLK – ...
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... ADSP-21992 SPISEL (OUTPUT) t SDSCIM SCLK (CPOL = 0) (OUTPUT) t SPICLM SCLK (CPOL = 1) (OUTPUT) MOSI (OUTPUT) t CPHA = 1 SSPID MISO (INPUT) MOSI (OUTPUT) t CPHA = 0 SSPID MSB MISO VALID (INPUT) t SPICHM t t SPICLK SPICLM t SPICHM t t DDSPID HDSPID MSB t t HSPID SSPID MSB VALID t DDSPID MSB ...
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... DSOE t SPISS Deassertion to Data High Impedance DSDHI t SCLK Edge to Data Out Valid (Data Out Delay) DDSPID t SCLK Edge to Data Out Invalid (Data Out Hold) HDSPID Min 1.6 2 Rev Page August 2007 ADSP-21992 Max Unit ns HCLK ns HCLK ns HCLK ns HCLK + 4 ns HCLK ns HCLK ...
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... ADSP-21992 SPISS (INPUT) t SPICHS SCLK (CPOL = 0) (INPUT) t SPICLS t SDSCI SCLK (CPOL = 1) (INPUT) t DSOE MISO (OUTPUT) CPHA = 1 MOSI (INPUT) t DSOE MISO (OUTPUT) CPHA = 0 MOSI (INPUT SPICLS SPICLK t SPICHS DDSPID HDSPID DDSPID MSB HSPID SSPID MSB VALID t DDSPID MSB t SSPID MSB LSB VALID VALID Figure 17. Serial Peripheral Interface (SPI) Port— ...
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... System inputs = DATA15–0, ADDR21–0, RD, WR, ACK, BR, BG, PF15–0, DR, TCLK, RCLK, TFS, RFS, CLKOUT, RESET. TCK TMS TDI TDO SYSTEM INPUTS SYSTEM OUTPUTS TCK t t STAP HTAP t DTDO t SSYS t DSYS Figure 18. JTAG Port Timing Rev Page August 2007 ADSP-21992 Min Max Unit TCK HSYS ...
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... ADSP-21992 POWER DISSIPATION Total power dissipation has two components, one due to inter- nal circuitry and one due to the switching of external output drivers. Internal power dissipation is dependent on the instruc- tion execution sequence and the data operands involved. The external component of total power dissipation is caused by the switching of output pins. Its magnitude depends on: • ...
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... EXAMPLE SYSTEM HOLD TIME CALCULATION To determine the data output hold time in a particular system, first calculate t on Page voltage of the ADSP-21992 and the input threshold for the device requiring the hold time. A typical ΔV will be 0 the total bus capacitance (per data line), and I t ENA age or three-state current (per data line) ...
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... ADSP-21992 PIN CONFIGURATIONS Table 28 identifies the signal for each CSP_BGA ball number. Table 29 identifies the CSP_BGA ball number for each signal name. Table 30 identifies the signal for each LQFP lead. Table 31 identifies the LQFP lead for each signal name. on Page 17 describes each signal. ...
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... VDDINT nc K12 EMU nc K13 TRST nc K14 TDO MS1 GND L4 VDDEXT TMR1 L5 VDDINT CONVST L6 VDDEXT CLKOUT L7 VDDINT Rev Page August 2007 ADSP-21992 Ball No. Signal L8 VDDINT L9 VDDEXT L10 VDDEXT L11 GND L12 BMODE2 L13 BMODE1 L14 CLKIN MS2 M4 GND M5 VDDEXT M6 GND M7 VDDEXT M8 CANRX ...
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... ADSP-21992 Table 29. 196-Ball CSP_BGA Ball Number by Signal Signal Ball No. Signal A0 N1 CLKOUT A1 N2 CML A2 M1 CONVST A10 H1 D7 A11 H2 D8 A12 G1 D9 A13 G2 D10 A14 F1 D11 A15 F2 D12 A16 E1 D13 A17 E2 D14 A18 D1 D15 A19 D2 DR ACK N11 EIA AL M10 EIB ...
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... PF14 nc 127 PF13 PWMSYNC 128 PF12 PWMPOL 129 GND PWMSR 130 nc PWMTRIP 131 nc GND 132 nc Rev Page August 2007 ADSP-21992 Lead No. Signal 133 VDDEXT 134 PF11 135 PF10 136 PF9 137 PF8 138 PF7/SPISEL7 139 PF6/SPISEL6 140 PF5/SPISEL5 141 PF4/SPISEL4 ...
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... ADSP-21992 Table 31. 176-Lead LQFP Lead Number by Signal Signal Lead No. Signal A0 50 CAPB A1 49 CAPT A10 35 CH A11 34 CL A12 33 CLKIN A13 30 CLKOUT A14 29 CML A15 28 CONVST A16 27 D0 A17 26 D1 A18 25 D10 A19 24 D11 A2 48 D12 A3 47 D13 A4 46 D14 A5 40 ...
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... DIMENSIONS COMPLY WITH JEDEC STANDARD MO-192 VARIATION AAE-1 WITH THE EXCEPTION OF MAXIMUM HEIGHT. 4. CENTER DIMENSIONS ARE NOMINAL. BSC SQ 13.00 BSC 1.00 BSC DETAIL A 0.75 0.70 0.65 0.57 0.52 0.20 0.47 MAX BALL COPLANARITY SEATING PLANE DETAIL A DIMENSIONS SHOWN IN MILLIMETERS Figure 22. 196-Ball CSP_BGA (BC-196-2) Rev Page August 2007 ADSP-21992 DETAIL ...
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... ADSP-21992 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW 176-LEAD LOW PROFILE QUAD FLAT PACKAGE [LQFP] ST-176 NOTES: 1. ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS IDEAL POSITION, WHEN MEASURED IN THE LATERAL DIRECTION. 2. CENTER DIMENSIONS ARE NOMINAL. 3. DIMENSIONS COMPLY WITH JEDEC STANDARD MS-026-BGA ...
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... ORDERING GUIDE Model Temperature Range ADSP-21992BBC – +85 C ADSP-21992YBC – +125 C ADSP-21992BST – + ADSP-21992BSTZ – +85 C ADSP-21992YST – +125 C 1 Referenced temperature is ambient temperature RoHS Complaint Part 1 Instruction Rate Operating Voltage Package Description Package Option 150 MHz 2.5 Int. V/3.3 Ext. V 150 MHz 2 ...
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... ADSP-21992 ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03163-0-8/07(A) Rev Page August 2007 ...