ADUC842BCPZ32-3 Analog Devices Inc, ADUC842BCPZ32-3 Datasheet - Page 59

• Manufacturer Part Number: ADUC842BCPZ32-3
• Description: Microconverter 1-cycle Version ADUC832
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC842BCPZ32-3

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 8.38MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: DMA, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MOSI is shared with P3.3 and, as such, has the same
configuration as the one shown in Figure 61.
BITS
SFR
MCO
MDE
I2C M
MCI
(MASTER/SLAVE)
SPE = 0 (I
HARDWARE SPI
Figure 64. SDATA/MOSI Pin I/O Functional Equivalent in SPI Mode
Figure 65. SDATA/MOSI Pin I/O Functional Equivalent in I
HARDWARE I
SPE = 0 (I
(SLAVE ONLY)
Figure 63. SCLOCK Pin I/O Functional Equivalent in I
HARDWARE I
(SLAVE ONLY)
BITS
MCO
I2C M
SFR
SPE = 1 (SPI ENABLE)
2
C ENABLE)
2
C ENABLE)
REJECTION FILTER
2
C
50ns GLITCH
REJECTION FILTER
2
C
50ns GLITCH
Q1
Q3
DV
DV
Q1
(OFF)
Q 3
DD
DD
Q2 (OFF)
Q4 (OFF)
DV
Q1
(OFF)
Q3
Q 2
Q 4
DD
SCLOCK
PIN
2
Q 2
Q 4
C Mode
SDATA/
2
MOSI
SDATA/
C Mode
PIN
MOSI
PIN
Rev. 0 | Page 59 of 88
Read-Modify-Write Instructions
Some 8051 instructions that read a port read the latch while
others read the pin. The instructions that read the latch rather
than the pins are the ones that read a value, possibly change it,
and then rewrite it to the latch. These are called read-modify-
write instructions, which are listed below. When the destination
operand is a port or a port bit, these instructions read the latch
rather than the pin.
Table 27. Read-Write-Modify Instructions
Instruction
ANL
ORL
XRL
JBC
CPL
INC
DEC
DJNZ
MOV PX.Y, C
CLR PX.Y
SETB PX.Y
1
Read-modify-write instructions are directed to the latch rather
than to the pin to avoid a possible misinterpretation of the
voltage level of a pin. For example, a port pin might be used to
drive the base of a transistor. When 1 is written to the bit, the
transistor is turned on. If the CPU then reads the same port bit
at the pin rather than the latch, it reads the base voltage of the
transistor and interprets it as a Logic 0. Reading the latch rather
than the pin returns the correct value of 1.
These instructions read the port byte (all 8 bits), modify the addressed bit,
and then write the new byte back to the latch.
1
1
1
Description
Logical AND, e.g., ANL P1, A
(Logical OR, e.g., ORL P2, A
(Logical EX-OR, e.g., XRL P3, A
Jump if Bit = 1 and clear bit, e.g., JBC P1.1,
LABEL
Complement bit, e.g., CPL P3.0
Increment, e.g., INC P2
Decrement, e.g., DEC P2
Decrement and Jump if Not Zero, e.g., DJNZ
P3, LABEL
Move Carry to Bit Y of Port X
Clear Bit Y of Port X
Set Bit Y of Port X
ADuC841/ADuC842/ADuC843