ADUC842BCPZ32-5 Analog Devices Inc, ADUC842BCPZ32-5 Datasheet - Page 21

• Manufacturer Part Number: ADUC842BCPZ32-5
• Description: Microconverter 1-cycle Version ADUC832
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC842BCPZ32-5

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 16.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: DMA, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ACCUMULATOR SFR (ACC)
ACC is the accumulator register and is used for math opera-
tions including addition, subtraction, integer multiplication and
division, and Boolean bit manipulations. The mnemonics for
accumulator-specific instructions refer to the accumulator as A.
B SFR (B)
The B register is used with the ACC for multiplication and
division operations. For other instructions, it can be treated as a
general-purpose scratchpad register.
Stack Pointer (SP and SPH)
The SP SFR is the stack pointer and is used to hold an internal
RAM address that is called the top of the stack. The SP register
is incremented before data is stored during PUSH and CALL
executions. While the stack may reside anywhere in on-chip
RAM, the SP register is initialized to 07H after a reset, which
causes the stack to begin at location 08H.
As mentioned earlier, the parts offer an extended 11-bit stack
pointer. The 3 extra bits used to make up the 11-bit stack
pointer are the 3 LSBs of the SPH byte located at B7H.
Data Pointer (DPTR)
The data pointer is made up of three 8-bit registers named DPP
(page byte), DPH (high byte), and DPL (low byte). These are
used to provide memory addresses for internal and external
code access and for external data access. They may be manipu-
lated as a 16-bit register (DPTR = DPH, DPL), although INC
DPTR instructions automatically carry over to DPP, or as three
independent 8-bit registers (DPP, DPH, DPL). The parts support
dual data pointers. Refer to the Dual Data Pointer section.
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Program Status Word (PSW)
The PSW SFR contains several bits reflecting the current status
of the CPU, as detailed in Table 5.
SFR Address
Power-On Default
Bit Addressable
Table 5. PSW SFR Bit Designations
Bit
7
6
5
4
3
2
1
0
Power Control SFR (PCON)
The PCON SFR contains bits for power-saving options and
general-purpose status flags, as shown in Table 6.
SFR Address
Power-On Default
Bit Addressable
Table 6. PCON SFR Bit Designations
Bit No.
7
6
5
4
3
2
1
0
Name
CY
AC
F0
RS1
RS0
OV
F1
P
Name
SMOD
SERIPD
INT0PD
ALEOFF
GF1
GF0
PD
IDL
ADuC841/ADuC842/ADuC843
Description
Double UART Baud Rate.
I
INT0 Power-Down Interrupt Enable.
Disable ALE Output.
General-Purpose Flag Bit.
General-Purpose Flag Bit.
Power-Down Mode Enable.
Idle Mode Enable.
2
C/SPI Power-Down Interrupt Enable.
Description
Carry Flag.
Auxiliary Carry Flag.
General-Purpose Flag.
Register Bank Select Bits.
RS1
0
0
1
1
Overflow Flag.
General-Purpose Flag.
Parity Bit.
RS0
0
1
0
1
D0H
00H
00H
No
Yes
87H
Selected Bank
0
1
2
3