AM29F016D-90EI Spansion Inc., AM29F016D-90EI Datasheet - Page 14

• Manufacturer Part Number: AM29F016D-90EI
• Description: Flash Memory IC
• Manufacturer: Spansion Inc.

Specifications of AM29F016D-90EI

• Memory Size: 16Mbit
• Memory Configuration: 2M X 8
• Ic Interface Type: Parallel
• Access Time: 90ns
• Memory Case Style: TSOP
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Termination Type: SMD
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Once V
p r e v i o u s l y
protected again. Figure 1 shows the algorithm, and
the Temporary Sector Group Unprotect diagram (Fig-
ure 16) shows the timing waveforms, for this feature.
Notes:
1. All protected sector groups unprotected.
2. All previously protected sector groups are protected
Figure 1. Temporary Sector Group Unprotect
once again.
ID
is removed from the RESET# pin, all the
p r o t e c t e d
Sector Group Unprotect
Program Operations
Completed (Note 2)
Operation
Perform Erase or
RESET# = V
RESET# = V
Temporary
(Note 1)
START
s e c t o r
ID
IH
g r o u p s
a r e
Am29F016D
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by spuri-
ous system level signals during V
power-down transitions, or from system noise.
Low V
When V
cept any write cycles. This protects data during V
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V
proper signals to the control pins to prevent uninten-
tional writes when V
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE#
= V
cle, CE# and WE# must be a logical zero while OE#
is a logical one.
Power-Up Write Inhibit
If WE# = CE# = V
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
IL
, CE# = V
CC
CC
Write Inhibit
is less than V
IH
IL
or WE# = V
LKO
and OE# = V
CC
. The system must provide the
is greater than V
LKO
, the device does not ac-
IH
. To initiate a write cy-
IH
during power up, the
CC
power-up and
LKO
.
13
CC
CC