CS42L51-CNZR Cirrus Logic Inc, CS42L51-CNZR Datasheet - Page 33

• Manufacturer Part Number: CS42L51-CNZR
• Description: IC LV Stereo Codec F/Digital Audio Apps
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS42L51-CNZR

• Data Interface: PCM Audio Interface
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 98 / 98
• Voltage - Supply, Analog: 1.8V, 2.5V
• Voltage - Supply, Digital: 1.8V, 2.5V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1005 - BOARD EVAL FOR CS42L51 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q3956082

DS679A2
4.4
4.4.1
Analog Outputs
AOUTA and AOUTB are the ground-centered line or headphone outputs. Various signal processing options
are available, including digital mixes with the ADC signal and an internal Beep Generator. The desired path
to the DAC must be selected using the DATA_SEL[1:0] bits.
Software
Controls:
INPUTS FROM ADCA
De-Emphasis Filter
The CODEC includes on-chip digital de-emphasis optimized for a sample rate of 44.1 kHz. The filter re-
sponse is shown in
that utilize 50/15 µs pre-emphasis equalization as a means of noise reduction. De-emphasis is only avail-
able in Single Speed Mode.
Digital Mix to ADC
Software
Controls:
Hardware
Control:
Serial Interface
and ADCB
DEEMPH
Demph
PCMMIXA_VOL[6:0]
PCMMIXB_VOL[6:0]
MUTE_PCMMIXA
MUTE_PCMMIXB
+12dB/-51.5dB
0.5dB steps
ADCMIXA_VOL[6:0]
ADCMIXB_VOL[6:0]
MUTE_ADCMIXA
MUTE_ADCMIXB
+12dB/-51.5dB
OFFTIME[2:0]
ONTIME[3:0]
0.5dB steps
“DAC Control (Address 09h)” on page
FREQ[3:0]
REPEAT
SIGNAL PROCESSING ENGINE (SPE)
VOL
BEEP
“DAC Control (Address 09h)” on page
Pin
“DEM” pin 4.
VOL
Generator
Beep
Figure
PCMA[1:0]
PCMB[1:0]
ADCA[1:0]
ADCB[1:0]
Channel
Swap
2.0dB steps
BPVOL[4:0]
0dB/-50dB
-10dB
Gain
0dB
dB
15. The de-emphasis feature is included to accommodate audio recordings
Channel
VOL
Swap
Σ
LO
HI
Setting
Figure 14. Output Architecture
Figure 15. De-Emphasis Curve
OUTA_VOL[7:0]
OUTB_VOL[7:0]
+12dB/-102dB
0.5dB steps
3.183 kHz
T1=50 µs
F1
Chnl Vol.
Settings
Σ
DAC_SNGVOL
DAC_SZC[1:0]
DACA_MUTE
DACB_MUTE
INV_DACA
INV_DACB
AMUTE
VOL
10.61 kHz
55.
F2
55.
TC_EN
BASS_CF[1:0]
TREB_CF[1:0]
Treble/
Control
+12.0dB/-10.5dB
T2 = 15 µs
Bass/
BASS[3:0]
TREB[3:0]
1.5dB steps
Frequency
ARATE[7:0]
RRATE[7:0]
MAX[2:0]
MIN[2:0]
LIM_SRDIS
LIM_ZCDIS
LIMIT_EN
Limiter
Detect
Peak
De-Emphasis Applied
No De-Emphasis
Selection
DATA_SEL[1:0]
10
01
00
Capacitor DAC
Switched
and Filter
PDN_DACA
PDN_DACB
CHRG_FREQ[3:0]
Headphone
Amp - GND
Centered
Charge
Pump
HP_GAIN[2:0]
CS42L51
Left/Right
HP Out
33