CS42L51-CNZR Cirrus Logic Inc, CS42L51-CNZR Datasheet - Page 42

• Manufacturer Part Number: CS42L51-CNZR
• Description: IC LV Stereo Codec F/Digital Audio Apps
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS42L51-CNZR

• Data Interface: PCM Audio Interface
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 98 / 98
• Voltage - Supply, Analog: 1.8V, 2.5V
• Voltage - Supply, Digital: 1.8V, 2.5V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1005 - BOARD EVAL FOR CS42L51 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q3956082

42
4.10
4.10.1 SPI Control
4.10.2 I²C Control
Software Mode
The control port is used to access the registers allowing the CODEC to be configured for the desired oper-
ational modes and formats. The operation of the control port may be completely asynchronous with respect
to the audio sample rates. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
The control port operates in 2 modes: SPI and I²C, with the CODEC acting as a slave device. SPI mode is
selected if there is a high-to-low transition on the AD0/CS pin after the RESET pin has been brought high.
I²C mode is selected by connecting the AD0/CS pin through a resistor to VL or DGND, thereby permanently
selecting the desired AD0 bit address state.
In SPI mode, CS is the
CS42L51 from the microcontroller), CDIN is the input data line from the microcontroller. Data is clocked
in on the rising edge of CCLK. The CODEC will only support write operations. Read request will be ig-
nored.
Figure 24
first seven bits on CDIN form the chip address and must be 1001010. The eighth bit is a read/write indi-
cator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP),
which is set to the address of the register that is to be updated. The next eight bits are the data which will
be placed into the register designated by the MAP.
There is MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero,
the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will autoincrement
after each byte is read or written, allowing block reads or writes of successive registers.
In I²C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.
There is no CS pin. Pin AD0 forms the least significant bit of the chip address and should be connected
through a resistor to VL or DGND as desired. The state of the pin is sensed while the
reset.
The signal timings for a read and write cycle are shown in
defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while
the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the
after a Start condition consists of a 7 bit chip address field and a R/W bit (high for a read, low for a write).
The upper 6 bits of the 7-bit address field are fixed at 100101. To communicate with a
address field, which is the first byte sent to the
the AD0 pin. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the
Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read,
CCLK
CDIN
CS
shows the operation of the control port in SPI mode. To write to a register, bring CS low. The
0
1
CHIP ADDRESS (WRITE)
1
0
2
0
3
1
4
0
CS42L51
Figure 24. Control Port Timing in SPI Mode
5
1
6
0
7
0
INCR
chip select signal, CCLK is the control port bit clock (input into the
8
9
6
10 11
MAP BYTE
5
4
12
3
CS42L51
13 14 15
2
1
0
16 17
, should match 100101 followed by the setting of
7
6
DATA
Figure 25
1
0
7
and
DATA +n
6
Figure
1
0
26. A Start condition is
CS42L51
CS42L51
CS42L51
DS679A2
, the chip
CS42L51
is being