CS4385-CQZR Cirrus Logic Inc, CS4385-CQZR Datasheet - Page 28

• Manufacturer Part Number: CS4385-CQZR
• Description: IC,D/A CONVERTER,OCTAL,24-BIT,QFP,48PIN
• Manufacturer: Cirrus Logic Inc

Specifications of CS4385-CQZR

• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 8
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 520mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1154 - BOARD EVAL FOR CS4385 DAC
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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4.8
Direct Stream Digital (DSD) Mode
In Software Mode, the DSD/PCM bits (Reg. 02h) are used to configure the device for DSD Mode. The
DSD_DIF bits (Reg 04h) then control the expected DSD rate and MCLK ratio.
The DIR_DSD bit (Reg 04h) selects between two proprietary methods for DSD-to-analog conversion. The
first method uses a decimation-free DSD processing technique which allows for features such as matched
PCM-level output, DSD volume control, and 50kHz on-chip filter. The second method sends the DSD data
directly to the on-chip switched-capacitor filter for conversion (without the above-mentioned features).
The DSD_PM_EN bit (Reg. 04h) selects Phase Modulation (data plus data inverted) as the style of data
input. In this mode, the DSD_PM_mode bit selects whether a 128Fs or 64x clock is used for phase modu-
lated 64x data (see
the CS4385, but may lower the sensitivity to board-level routing of the DSD data signals.
The CS4385 can detect errors in the DSD data which does not comply with the SACD specification. The
STATIC_DSD and INVALID_DSD bits (Reg. 04h) allow the CS4385 to alter the incoming invalid DSD data.
Depending on the error, the data may either be attenuated or replaced with a muted DSD signal (the
MUTEC pins would be set according to the DAMUTE bit (Reg. 08h)).
More information for any of these register bits can be found in
The DSD input structure and analog outputs are designed to handle a nominal 0 dB-SACD (50% modulation
index) at full rated performance. Signals of +3 dB-SACD may be applied for brief periods of time, however;
performance at these levels is not guaranteed. If sustained +3 dB-SACD levels are required, the digital vol-
ume control should be set to -3.0 dB. This same volume control register affects PCM output levels. There
is no need to change the volume control setting between PCM and DSD in order to have the 0dB output
levels match (both 0 dBFS and 0 dB-SACD will output at -3 dB in this case).
(64Fs)
BCKA
DSD Normal Mode
DSD_SCLK
Not Used
Not Used
DSDAx,
DSDBx
Figure
Figure 22. DSD Phase Modulation Mode Diagram
D0
D0
22). Use of Phase Modulation Mode may not directly affect the performance of
D1
D1
D1
Section 7. “Filter Plots” on page
D2
D2
DSDAx,
DSD_SCLK
DSD_SCLK
DSDBx
Not Used
Modulation Mode
DSD Phase
CS4385
48.
(64Fs)
BCKD
(128Fs)
DS671F2
BCKA