CS4525-CNZR Cirrus Logic Inc, CS4525-CNZR Datasheet - Page 55

IC PWM Controller+power Stage

CS4525-CNZR

Manufacturer Part Number
CS4525-CNZR
Description
IC PWM Controller+power Stage
Manufacturer
Cirrus Logic Inc
Series
Popguard®r
Type
Class Dr
Datasheet

Specifications of CS4525-CNZR

Output Type
2-Channel (Stereo) or 4-Channel (Quad)
Max Output Power X Channels @ Load
30W x 1 @ 4 Ohm; 15W x 2 @ 8 Ohm
Voltage - Supply
8 V ~ 18 V
Features
ADC, Depop, I²C, I²S, Mute, PWM, Short-Circuit and Thermal Protection, Volume Control
Mounting Type
Surface Mount
Package / Case
48-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1586 - REFERENCE BOARD FOR CS4525 PWM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS4525-CNZR
Manufacturer:
CIRRUSLOGICINC
Quantity:
20 000
DS726PP3
6.2.3
6.2.4
6.2.2.2
1. Bring MUTE low to mute the device’s outputs and minimize audible pops.
2. Bring RST low to halt the operation of the device.
3. The SYS_CLK signal may now be removed. See
4. Remove power.
Input Source Selection
The CS4525 can accept analog or digital audio input signals. Digital audio input signals are supplied
through the serial audio input port as outlined in
signals are supplied through the internal ADC as outlined in
is selected by the ADC/SP pin as shown in
ing any audible pops or clicks.
In hardware mode, the serial audio input port supports both I²S and left-justified formats. The serial audio
interface format is selected by the I2S/LJ pin as shown in
PWM Channel Delay
In hardware mode, the CS4525 offsets the PWM switching edges between channels as a method of man-
aging switching noise and reducing radiated emissions.
The OUT3/OUT4 signal pair is delayed from the OUT1/OUT2 signal pair by 4 SYS_CLK cycles as shown
in
Figure 23
The device’s power consumption will be brought to an absolute minimum.
ADC/SP
I2S/LJ
High
High
Low
Low
Power-Down Sequence
below. The absolute delay time is calculated by multiplying the period SYS_CLK by 4.
Figure 23. Hardware Mode PWM Output Delay
OUT2
OUT1
OUT3
OUT4
Table 15. Serial Audio Interface Format Selection
Table 14. Input Source Selection
Table 14
Selected Serial Audio Interface Format
4 x T
“Serial Audio Interfaces” on page
Digital Audio Inputs (Serial Port)
Analog Audio Inputs (ADC)
SYS_CLK
Selected Input Source
below and can be changed at any time without caus-
section 6.2.1
Left-Justified
Table 15
“Analog Inputs” on page
I²S
on
below.
page 54
for more information.
62. Analog audio input
61. The input source
CS4525
55

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