CS4954-CQZR Cirrus Logic Inc, CS4954-CQZR Datasheet - Page 27

• Manufacturer Part Number: CS4954-CQZR
• Description: IC NTSC/PAL Digital Video Encoder
• Manufacturer: Cirrus Logic Inc
• Type: Video Encoderr

Specifications of CS4954-CQZR

• Voltage - Supply, Analog: 3.15 V ~ 5.25 V
• Voltage - Supply, Digital: 3.15 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CDB4955A - EVALUATION BOARD FOR CS4955A
• Applications: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 6. Internal Color Bar Values (8-bit values, Cb/Cr are in
5.13
VBI (Vertical Blanking Interval) encoding is per-
formed according to SMPTE RP 188 recommenda-
tions. In NTSC mode, lines 10 - 20 and lines 272 -
In PAL mode lines 6 - 22 and lines 318 -335 are
used. The VBI encoding mode can be set through
the CONTROL_3 register.
All digital input data is passed through the chip
when this mode is enabled. It is therefore the re-
sponsibility of the user to ensure appropriate ampli-
tude levels. Table
digital input signal and the analog output voltage.
Each LSB corresponds to a step of 5 mV in the out-
put voltage.
5.14
The ITU-R BT.601 recommendation limits the al-
lowed range for the digital video data between
0×10 - 0×EB for luma and between 0×10 - 0×F0 for
the chrominance values. This chip will clip any
DS278F6
White
Yellow
Cyan
Green
Magenta
Red
Blue
Black
283 are used for the transmission of ancillary data.
Color
Digital Input
Table 7. VBI Encoding Signal Amplitudes
VBI encoding
Super White/Super Black support
0
0
0
×
×
×
3B
C4
38
twos complement format)
7
shows the relationship of the
+ 28
+ 56
+ 84
- 84
- 56
- 28
Cb
0
0
Analog Output Voltage
+ 14
+ 70
+ 84
- 84
- 70
- 14
Cr
1000 mV
0
0
286 mV
300 mV
+ 167
+ 156
+ 138
+ 127
+ 110
+ 99
+ 81
+ 70
Y
digital input value which is out of this range to con-
form to the ITU-R BT.601 specifications.
However for some applications it is useful to allow
a wider input range. By setting the CLIP_OFF bit
(CONTROL_6 register), the allowed input range is
extended to 0×01 - 0×FE for both luma and chromi-
nance values.
Note that 0×00 and 0×FF values are never allowed,
since they are reserved for synchronization infor-
mation.
5.15
In order to better support precise video mode
switches and to establish a software/hardware
handshake with the closed caption insertion block,
the CS4954/5 is equipped with an interrupt pin
named INT. The INT pin is active high. There are
three interrupt sources: VSYNC, Line 21, and Line
284. Each interrupt can be individually disabled
with the INT_EN Register. Each interrupt is also
cleared via writing a one to the corresponding
INT_CLR Register bits. The three individual inter-
rupts are OR-ed together to generate an interrupt
signal which is presented on the INT output pin. If
an interrupt has occurred, it cannot be eliminated
with a disable, it must be cleared.
5.16
The CS4954/5 has a GPIO port and register that is
available when the device is configured for I²C host
interface operation. In I²C host interface mode, the
PDAT [7:0] pins are unused by the host interface
and they can operate as input or output pins for the
GPIO_DATA_REG
CS4954/5 also contains the GPIO_CTRL_REG
Register (0×09) which is used to configure the
GPIO pins for input or output operation.
The GPIO port PDAT [7:0] pins are configured for
input
GPIO_CTRL_REG [7:0] bits are set to 0. In GPIO
input mode, the CS4954/5 will latch the data on the
PDAT [7:0] pins into the corresponding bit loca-
Interrupts
General Purpose I/O Port
operation
when
Register
CS4954 CS4955
the
(0×0A).
corresponding
The
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