CS5526-BSZR Cirrus Logic Inc, CS5526-BSZR Datasheet - Page 17

• Manufacturer Part Number: CS5526-BSZR
• Description: IC 20-Bit Delta Sigma Multi-Range ADC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5526-BSZR

• Number Of Bits: 20
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 12.7mW
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1014 - EVAL BOARD FOR CS5526
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The offset and gain calibration steps each take one
conversion cycle to complete. At the end of the cal-
ibration step, the calibration control bits will be set
back to logic 0, and the DF (Done Flag) bit will be
set to a logic 1. For the combination self-calibra-
tion (CC2-CC0= 011; offset followed by gain), the
calibration will take two conversion cycles to com-
plete and will set the DF bit after the gain calibra-
tion is completed. The DF bit will be cleared any
time the data register, the offset register, the gain
register, or the setup register is read. Reading the
configuration register alone will not clear the DF
bit.
Self Calibration
The CS5525/26 offer both self offset and self gain
calibrations. For the self-calibration of offset in the
25 mV, 55 mV, and 100 mv ranges, the converter
internally ties the inputs of the instrumentation am-
plifier together and routes them to the AIN- pin as
shown in Figure 10. For proper self-calibration of
offset to occur in the 25 mV, 55 mV, and 100 mV
ranges, the AIN- pin must be at the proper com-
mon-mode-voltage (i.e. AIN- = 0V, NBV must be
between -1.8 V to -2.5 V). For self-calibration of
offset in the 1.0 V, 2.5 V, and 5 V ranges, the inputs
DS202F5
Offset Register
One LSB represents 2
Offset and data word bits align by MSB (bit MSB-4 of offset register changes bit MSB-4 of data)
Gain Register
The gain register span is from 0 to (2-2
Register
Reset (R)
Register
Reset (R)
MSB
MSB
Sign
2
1
0
0
2
-24
2
0
0
-1
-2
proportion of the input span (bipolar span is 2 times unipolar span)
2
2
0
0
-2
-3
2
2
0
-3
0
-4
Table 4. Offset and Gain Registers
-23
2
). After Reset the MSB = 1, all other bits are 0.
2
0
0
-4
-5
2
2
0
0
-5
-6
Table 3.
of the modulator are connected together and then
routed to the VREF- pin as shown in Figure 11.
For self-calibration of gain, the differential inputs
of the modulator are connected to VREF+ and
2
2
-18
0
-19
0
Figure 11. Self Calibration of Offset (High Ranges).
Figure 10. Self Calibration of Offset (Low Ranges).
AIN+
AIN-
2
2
-19
0
VREF-
-20
0
AIN+
AIN-
OPEN
CLOSED
S1
S2
2
2
-20
0
-21
0
2
+
-
2
-21
0
-22
0
X20
+
-
CS5525 CS5526
X20
2
2
-22
0
-23
0
CLOSED
OPEN
OPEN
S4
S2
S1
LSB
2
LSB
2
-23
0
-24
0
+
-
+
-
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