CY62256VNLL-70SNXET Cypress Semiconductor Corp, CY62256VNLL-70SNXET Datasheet - Page 5

• Manufacturer Part Number: CY62256VNLL-70SNXET
• Description: CY62256VNLL-70SNXET
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY62256VNLL-70SNXET

• Format - Memory: RAM
• Memory Type: SRAM
• Memory Size: 256K (32K x 8)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Characteristics
Document #: 001-06512 Rev. *B
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
Notes
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
7. Test conditions assume signal transition time of 5 ns or less timing reference levels of V
8. At any given temperature and voltage condition, t
9. t
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
and 100-pF load capacitance.
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
HZOE
, t
HZCE
Parameter
[10, 11]
, and t
HZWE
are specified with C
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
CE LOW to Low-Z
CE HIGH to High-Z
CE LOW to Power Up
CE HIGH to Power Down
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z
WE HIGH to Low-Z
Over the Operating Range
L
= 5 pF as in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
HZCE
is less than t
[8]
[8]
[8, 9]
[8, 9]
[8, 9]
[8]
Description
LZCE
, t
HZOE
[7]
is less than t
CC
/2, input pulse levels of 0 to V
HZWE
LZOE
and t
, and t
SD
.
HZWE
is less than t
Min
70
10
10
70
60
60
50
30
10
5
0
0
0
0
CY62256VN-70
CC
, and output loading of the specified I
LZWE
for any given device.
Max
70
70
35
25
25
70
25
CY62256VN
Page 5 of 13
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OL
/I
OH
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