CY7B991V-5JXIT Cypress Semiconductor Corp, CY7B991V-5JXIT Datasheet - Page 11

• Manufacturer Part Number: CY7B991V-5JXIT
• Description: IC,Eight Distributed-Output Clock Driver,LDCC,32PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp
• Series: RoboClock™r
• Type: Buffer/Driverr

Specifications of CY7B991V-5JXIT

• Number Of Circuits: 1
• Ratio - Input:output: 8:8
• Differential - Input:output: Yes/Yes
• Input: 3-State
• Output: LVTTL
• Frequency - Max: 80MHz
• Voltage - Supply: 2.97 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-PLCC
• Frequency-max: 80MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Characteristics – 5 Option
Over the Operating Range
Notes
Document Number: 38-07141 Rev. *G
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
10. Test measurement levels for the CY7B991V are TTL levels (1.5 V to 1.5 V). Test conditions assume signal transition times of 2 ns or less and output loading as shown
11. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
12. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same t
13. t
14. t
15. C
16. There are three classes of outputs: Nominal (multiple of t
17. t
18. t
19. Specified with outputs loaded with 30 pF for the CY7B991V–5 and –7 devices. Devices are terminated through 50Ω to V
20. t
21. t
NOM
RPWH
RPWL
U
SKEWPR
SKEW0
SKEW1
SKEW2
SKEW3
SKEW4
DEV
PD
ODCV
PWH
PWL
ORISE
OFALL
LOCK
JR
Parameter
in the AC Test Loads and Waveforms unless otherwise specified.
loaded with 30 pF and terminated with 50Ω to V
or Divide-by-4 mode).
is measured at 0.8 V.
measured from the application of a new signal or frequency at REF or FB until t
SKEWPR
SKEW0
DEV
ODCV
ORISE
LOCK
L
=0 pF. For C
is the output-to-output skew between any two devices operating under the same conditions (V
is the time that is required before synchronization is achieved. This specification is valid only after V
is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in t
and t
is defined as the skew between outputs when they are selected for 0t
is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0t
OFALL
Operating clock frequency in MHz
REF pulse width HIGH
REF pulse width LOW
Programmable skew unit
Zero output matched-pair skew (XQ0, XQ1)
Zero output skew (all outputs)
Output skew (rise-rise, fall-fall, same class outputs)
Output skew (rise-fall, nominal-inverted, divided-divided)
Output skew (rise-rise, fall-fall, different class outputs)
Output skew (rise-fall, nominal-divided, divided-inverted)
Device-to-device skew
Propagation delay, REF rise to FB rise
Output duty cycle variation
Output HIGH time deviation from 50%
Output LOW time deviation from 50%
Output rise time
Output fall time
PLL lock time
Cycle-to-cycle output jitter
L
=30 pF, t
measured between 0.8 V and 2.0 V.
SKEW0
= 0.35 ns.
[2, 10]
[21]
[20, 21]
[20, 21]
[12, 18]
CC
/2 (CY7B991V).
[19]
[[13, 14]
Description
U
delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2
[20]
[20]
FS = LOW
FS = MID
FS = HIGH
RMS
Peak-to-peak
[13, 14]
U
. Other outputs are divided or inverted but not shifted.
PD
[12]
is within specified limits.
[1, 2]
[13, 17]
[1, 2]
[1, 2]
[13, 17]
[12]
[13, 17]
[13, 17]
CC
ambient temperature, air flow, etc.)
SKEW2
CC
is stable and within normal operating limits. This parameter is
and t
U
.
SKEW4
–0.5
–1.0
0.15
0.15
Min
5.0
5.0
15
25
40
–
–
–
–
–
–
–
–
–
–
–
–
specifications.
CY7B991V–5
U
CC
delay has been selected when all are
/2. t
0.25
Typ
0.1
0.6
0.5
0.5
0.5
0.0
0.0
1.0
1.0
–
–
–
–
–
–
–
–
–
–
–
PWH
See
is measured at 2.0 V. t
Table 2
Max
0.25
1.25
+0.5
+1.0
200
0.5
0.7
1.0
0.7
1.0
2.5
1.5
1.5
0.5
30
50
80
25
–
–
3
CY7B991V
Page 11 of 17
MHz
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
PWL
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