CY7C1471V33-133AXC Cypress Semiconductor Corp, CY7C1471V33-133AXC Datasheet
CY7C1471V33-133AXC
Specifications of CY7C1471V33-133AXC
CY7C1471V33-133AXC
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CY7C1471V33-133AXC Summary of contents
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... Document Number: 38-05288 Rev. *L 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Functional Description The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are 3 × 36/4 M × 18/1 M × 72 synchronous flow through burst SRAMs designed specifically to support unlimited true back-to-back read or write operations without the insertion of wait states ...
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... Logic Block Diagram – CY7C1471V33 (2 M × 36) ADDRESS A0, A1, A REGISTER MODE CE CLK C CEN ADV/ READ LOGIC CE1 CE2 CE3 ZZ Logic Block Diagram – CY7C1473V33 (4 M × 18) ADDRESS A0, A1, A REGISTER MODE CE CLK ADV/ CE1 CE2 CE3 ZZ Document Number: 38-05288 Rev A1 A0 BURST ...
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... MODE CLK C CEN WRITE ADDRESS REGISTER 1 ADV/ READ LOGIC CE1 CE2 CE3 ZZ Sleep Control Document Number: 38-05288 Rev A1 A0' BURST D0 Q0 LOGIC ADV/LD C WRITE ADDRESS REGISTER 2 MEMORY WRITE DRIVERS WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC REGISTER 1 CY7C1471V33 CY7C1473V33 CY7C1475V33 ARRAY ...
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... TAP REGISTERS ...................................................... 16 TAP Instruction Set ................................................... 16 TAP Timing ...................................................................... 17 TAP AC Switching Characteristics ............................... 18 3.3 V TAP AC Test Conditions ....................................... 19 3.3 V TAP AC Output Load Equivalent ......................... 19 Document Number: 38-05288 Rev. *L CY7C1471V33 CY7C1473V33 CY7C1475V33 2.5 V TAP AC Test Conditions ....................................... 19 2.5 V TAP AC Output Load Equivalent ......................... 19 TAP DC Electrical Characteristics and Operating Conditions ..................................................... 19 Scan Register Sizes ...
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... Selection Guide Maximum access time Maximum operating current Maximum CMOS standby current Document Number: 38-05288 Rev. *L CY7C1471V33 CY7C1473V33 CY7C1475V33 133 MHz 117 MHz 6.5 8.5 305 275 120 120 Unit Page [+] Feedback ...
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... Pin Configurations DQP DDQ BYTE DDQ DDQ BYTE DDQ DQP 30 D Document Number: 38-05288 Rev. *L 100-pin TQFP Pinout CY7C1471V33 CY7C1471V33 CY7C1473V33 CY7C1475V33 80 DQP DDQ BYTE DDQ DDQ BYTE DDQ DQP A Page [+] Feedback ...
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... Pin Configurations (continued DDQ DDQ BYTE DDQ DQP DDQ Document Number: 38-05288 Rev. *L 100-pin TQFP Pinout CY7C1473V33 CY7C1471V33 CY7C1473V33 CY7C1475V33 DDQ DQP DDQ BYTE DDQ DDQ Page [+] Feedback ...
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... DDQ DDQ N DQP DDQ P NC/144M MODE NC/576M NC/1G A CE2 DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ P NC/144M MODE A A Document Number: 38-05288 Rev. *L CY7C1471V33 (2 M × 36 CEN CLK TDO A TDI A0 A TCK TMS CY7C1473V33 (4 M × 18) ...
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... CEN DDQ DDQ DDQ MODE TDI CY7C1471V33 CY7C1473V33 CY7C1475V33 DQb DQb 3 BWS BWS DQb DQb b f BWS BWS DQb DQb DQb DQb DQPf DQPb DDQ DDQ V DQf V DQf DQf DQf DDQ DDQ V V DQf SS SS DQf V V DDQ DQf DQf DDQ NC ...
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... CE to select or deselect the device and CE to select or deselect the device and CE to select or deselect the device and DQP s is controlled by BW correspondingly CY7C1471V33 CY7C1473V33 CY7C1475V33 are placed in a tri-state condition.The X . During s or left floating selects DD Page [+] Feedback ...
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... connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address expansion pins and are not internally connected to the die. Functional Overview The CY7C1471V33, CY7C1473V33, and CY7C1475V33 are synchronous flow through burst SRAMs designed specifically to eliminate wait states during ...
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... OE. Burst Write Accesses The CY7C1471V33, CY7C1473V33, and CY7C1475V33 have an on-chip burst counter that enables the user to supply a single address and conduct up to four write operations without reasserting the address inputs. ADV/LD must be driven LOW to ...
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... Truth Table The truth table for CY7C1471V33, CY7C1473V33, CY7C1475V33 follows. Address Operation Used Deselect cycle None Deselect cycle None Deselect cycle None Continue deselect cycle None Read cycle External (begin burst) Read cycle Next (continue burst) NOP/dummy read External (begin burst) ...
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... Truth Table for Read/Write The read-write truth table for CY7C1471V33 follows. Function Read Write no bytes written Write byte A – (DQ and DQP ) A A Write byte B – (DQ and DQP ) B B Write byte C – (DQ and DQP ) C C Write byte D – (DQ and DQP ) D D Write all bytes Truth Table for Read/Write The read-write truth table for CY7C1473V33 follows ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1471V33, CY7C1473V33, and CY7C1475V33 incorporate a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM ...
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... Capture-DR state, an input or output may undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but CY7C1471V33 CY7C1473V33 CY7C1475V33 Page [+] Feedback ...
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... BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions TDIS t TDIH t TDOX DON’ UNDEFINED CY7C1471V33 CY7C1473V33 CY7C1475V33 TDOV Page [+] Feedback ...
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... Notes 12.t and t refer to the setup and hold time requirements of latching data from the boundary scan register 13.Test conditions are specified using the load in TAP AC Test Conditions. t Document Number: 38-05288 Rev. *L Description / ns CY7C1471V33 CY7C1473V33 CY7C1475V33 Min Max Unit 50 – ns – 20 MHz 20 – ...
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... DDQ I = 100 µ 3 DDQ V = 2.5 V DDQ V = 3.3 V DDQ V = 2.5 V DDQ V = 3.3 V DDQ V = 2.5 V DDQ GND < V < DDQ CY7C1471V33 CY7C1473V33 CY7C1475V33 to 2 1.25V 50Ω 50Ω 20pF O Min Max Unit 2.4 – V 2.0 – V 2.9 – V 2.1 – V – 0.4 V – 0.4 V – ...
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... Bit Size (× 36) Bit Size (× 18 Description CY7C1471V33 CY7C1473V33 CY7C1475V33 Description Describes the version number Reserved for internal use Defines memory type and architecture Defines width and density Enables unique identification of SRAM vendor Indicates the presence register Bit Size (× 72) ...
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... L10 59 B8 K11 60 A7 165-ball ID Bit # 165-ball L10 P6 28 K10 R6 29 J10 R8 30 H11 P3 31 G11 P4 32 F11 P8 33 E11 P9 34 D11 P10 35 C11 R9 36 A11 R10 37 A9 R11 38 B9 M10 39 A10 CY7C1471V33 CY7C1473V33 CY7C1475V33 Bit # 165-ball Bit # 165-ball ID 40 B10 ...
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... J11 V5 72 J10 U5 73 H11 U6 74 H10 W7 75 G11 V7 76 G10 U7 77 F11 V8 78 F10 V9 79 E10 W11 80 E11 W10 81 D11 V11 82 D10 V10 83 C11 U11 84 C10 CY7C1471V33 CY7C1473V33 CY7C1475V33 Bit # 209-ball ID 85 B11 86 B10 87 A11 88 A10 100 B3 101 C3 102 C4 103 ...
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... Max, device deselected, All Speeds V 0.3 V, – 0 /2). Undershoot: V (AC) > –2 V (pulse width less than t CYC IL (min) within 200 ms. During this time V < V and CY7C1471V33 CY7C1473V33 CY7C1475V33 + 0 Ambient V V Temperature DD DDQ 0 C to +70 C 3.3 V– 2.5 V – 10 ...
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... EIA/JESD51 317 3 DDQ GND 351 INCLUDING JIG AND (b) SCOPE R = 1667 2 DDQ GND 1538 INCLUDING JIG AND (b) SCOPE CY7C1471V33 CY7C1473V33 CY7C1475V33 165 FBGA 209 BGA Unit Package Package ...
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... V of“AC Test Loads and Waveforms” on page and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ CY7C1471V33 CY7C1473V33 CY7C1475V33 = 3.3 V and is DDQ unless otherwise noted. 117 MHz Unit ...
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... CDV t DOH t OEV t CLZ D(A2+1) Q(A3) Q(A4) t OEHZ t OELZ READ READ BURST Q(A3) Q(A4) READ Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH CY7C1471V33 CY7C1473V33 CY7C1475V33 CHZ Q(A4+1) D(A5) Q(A6) D(A7) t DOH W RITE READ W RITE DESELECT D(A5) Q(A6) D(A7) is LOW HIGH ...
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... The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle. Document Number: 38-05288 Rev. *L [25, 26, 27 Q(A2) Q(A3) STALL READ WRITE STALL Q(A3) D(A4) DON’T CARE UNDEFINED is LOW. When CE is HIGH HIGH CY7C1471V33 CY7C1473V33 CY7C1475V33 CHZ D(A4) Q(A5) t DOH NOP READ DESELECT CONTINUE Q(A5) DESELECT is LOW HIGH Page ...
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... DQs are in high-Z when exiting ZZ sleep mode. Document Number: 38-05288 Rev. *L [28, 29] Figure 3. ZZ Mode Timing High-Z DON’T CARE “Truth Table” on page 13 for all possible signal conditions to deselect the device. CY7C1471V33 CY7C1473V33 CY7C1475V33 t ZZREC t RZZI DESELECT or READ Only Page [+] Feedback ...
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... To find the office closest to you, visit http://www.cypress.com/go/datasheet/offices. Speed Package (MHz) Ordering Code Diagram 133 CY7C1471V33-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free Ordering Code Definitions CY7C 1471 V33 - 133 AX C Document Number: 38-05288 Rev. *L http://www.cypress.com/products ...
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... Package Diagrams Figure 4. 100-pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm), 51-85050 Document Number: 38-05288 Rev. *L CY7C1471V33 CY7C1473V33 CY7C1475V33 51-85050 *C Page [+] Feedback ...
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... Package Diagrams (continued) Figure 5. 165-ball FBGA (15 × 17 × 1.4 mm), 51-85165 Document Number: 38-05288 Rev. *L CY7C1471V33 CY7C1473V33 CY7C1475V33 51-85165 *B Page [+] Feedback ...
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... Package Diagrams (continued) Figure 6. 209-ball FBGA (14 × 22 × 1.76 mm), 51-85167 Document Number: 38-05288 Rev. *L CY7C1471V33 CY7C1473V33 CY7C1475V33 51-85167 *A Page [+] Feedback ...
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... TCK test clock TMS test mode select TDI test data-in TDO test data-out TQFP thin quad flat pack WE write enable Document Number: 38-05288 Rev. *L CY7C1471V33 CY7C1473V33 CY7C1475V33 Document Conventions Units of Measure Symbol Unit of Measure ns nano seconds V Volts µA micro Amperes mA ...
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... Document History Page Document Title: CY7C1471V33/CY7C1473V33/CY7C1475V33, 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Flow-through SRAM with NoBL™ Architecture Document Number: 38-05288 Submission REV. ECN NO. Orig. of Change Date ** 114675 08/06/02 *A 121521 02/07/03 *B 223721 See ECN *C 235012 See ECN *D 243572 See ECN ...
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... Document Title: CY7C1471V33/CY7C1473V33/CY7C1475V33, 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Flow-through SRAM with NoBL™ Architecture Document Number: 38-05288 Submission REV. ECN NO. Orig. of Change Date *I 472335 See ECN *J 1274732 See ECN VKN/AESA *K 2898501 03/24/2010 *L 3034798 09/21/2010 Document Number: 38-05288 Rev. *L Description of Change ...
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... Document Number: 38-05288 Rev. *L NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised September 21, 2010 CY7C1471V33 CY7C1473V33 CY7C1475V33 PSoC Solutions psoc.cypress.com/solutions ...