CY7C1471V33-133AXC Cypress Semiconductor Corp, CY7C1471V33-133AXC Datasheet - Page 20

• Manufacturer Part Number: CY7C1471V33-133AXC
• Description: SRAM (Static RAM)
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1471V33-133AXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Density: 72Mb
• Access Time (max): 6.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 21b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 305mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 2M
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2167; CY7C1471V33-133AXC

Identification Register Definitions
Scan Register Sizes
Identification Codes
Note
Document Number: 38-05288 Rev. *L
Revision number (31:29)
Device depth (28:24)
Architecture/memory type(23:18)
Bus width/density(17:12)
Cypress JEDEC ID code (11:1)
ID register presence indicator (0)
Instruction
Bypass
ID
Boundary scan order – 165FBGA
Boundary scan order – 209BGA
EXTEST
IDCODE
SAMPLE Z
RESERVED
SAMPLE/PRELOAD
RESERVED
RESERVED
BYPASS
15. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
Instruction Field
Instruction
Register Name
[15]
Code
000
001
010
100
101
011
110
111
CY7C1471V33
00000110100
(2 M × 36)
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to high Z state. This instruction is not 1149.1-compliant.
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a high Z state.
Do Not Use: This instruction is reserved for future use.
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
001001
100100
01011
000
1
Bit Size (× 36)
32
71
3
1
-
CY7C1473V33
00000110100
(4 M × 18)
001001
010100
01011
000
1
CY7C1475V33
00000110100
Bit Size (× 18)
(1 M × 72)
001001
110100
Description
01011
000
1
32
52
3
1
-
Describes the version number
Reserved for internal use
Defines memory type and architecture
Defines width and density
Enables unique identification of SRAM
vendor
Indicates the presence of an ID
register
Description
Bit Size (× 72)
CY7C1471V33
CY7C1473V33
CY7C1475V33
110
32
3
1
-
Page 20 of 36
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