CY7C4245-10AXI Cypress Semiconductor Corp, CY7C4245-10AXI Datasheet - Page 4

• Manufacturer Part Number: CY7C4245-10AXI
• Description: CY7C4245-10AXI
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4245-10AXI

• Function: Synchronous
• Memory Size: 72K (4K x 18)
• Data Rate: 100MHz
• Access Time: 8ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Definitions
Architecture
The CY7C42X5 consists of an array of 64 to 4K words of 18 bits
each (implemented by a dual-port array of SRAM cells), a read
pointer, a write pointer, control signals (RCLK, WCLK, REN,
WEN, RS), and flags (EF, PAE, HF, PAF, FF). The CY7C42X5
also includes the control signals WXI, RXI, WXO, RXO for depth
expansion.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS) cycle.
This causes the FIFO to enter the Empty condition signified by
EF being LOW. All data outputs go LOW after the falling edge of
RS only if OE is asserted. In order for the FIFO to reset to its
default state, a falling edge must occur on RS and the user must
not read or write while RS is LOW.
FIFO Operation
When the WEN signal is active (LOW), data present on the D
pins is written into the FIFO on each rising edge of the WCLK
signal. Similarly, when the REN signal is active LOW, data in the
FIFO memory will be presented on the Q
will be presented on each rising edge of RCLK while REN is
active LOW and OE is LOW. REN must set up t
for it to be a valid read function. WEN must occur t
WCLK for it to be a valid write function.
An Output Enable (OE) pin is provided to three-state the Q
outputs when OE is deasserted. When OE is enabled (LOW),
data in the output register will be available to the Q
after t
output data on the FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional writes
when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q
after additional reads occur.
Note:
Document Number: 001-45652 Rev. *A
RXO
RS
OE
V
1. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK.
Signal Name
CC
/SMODE
OE
. If devices are cascaded, the OE function will only
Read Expansion
Output
Reset
Output Enable
Synchronous
Almost Empty/
Almost Full Flags
Description
(continued)
IO
O
I
I
I
0−17
Cascaded – Connected to RXI of next device.
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected.
If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
Dual-Mode Pin. Asynchronous Almost Empty/Almost Full flags – tied to V
Synchronous Almost Empty/Almost Full flags – tied to V
nized to RCLK, Almost Full synchronized to WCLK.)
outputs. New data
0−17
ENS
before RCLK
outputs even
0−17
ENS
outputs
before
0-17
0–17
Programming
The CY7C42X5 devices contain two 12-bit offset registers. Data
present on D
distance from Empty (Full) that the Almost Empty (Almost Full)
flags become active. If the user elects not to program the FIFO’s
flags, the default offset values are used (see
Load LD pin is set LOW and WEN is set LOW, data on the inputs
D
LOW-to-HIGH transition of the write clock (WCLK). When the LD
pin and WEN are held LOW then data is written into the Full offset
register on the second LOW-to-HIGH transition of the Write
Clock (WCLK). The third transition of the Write Clock (WCLK)
again writes to the Empty offset register (see
offset registers does not have to occur at one time. One or two
offset registers can be written and then, by bringing the LD pin
HIGH, the FIFO is returned to normal read/write operation. When
the LD pin is set LOW, and WEN is LOW, the next offset register
in sequence is written.
The contents of the offset registers can be read on the output
lines when the LD pin is set LOW and REN is set LOW; then,
data can be read on the LOW-to-HIGH transition of the Read
Clock (RCLK).
Table 1. Write Offset Register
LD
0–11
0
0
1
1
is written into the Empty offset register on the first
WEN
0
1
0
1
0–11
Function
WCLK
during a program write will determine the
[1]
Writing to offset registers:
Empty Offset
Full Offset
No Operation
Write Into FIFO
No Operation
CY7C4425/4205/4215
CY7C4225/4235/4245
SS
. (Almost Empty synchro-
Selection
Table
Table
CC
2). When the
1). Writing all
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