CY8C3246LTI-125 Cypress Semiconductor Corp, CY8C3246LTI-125 Datasheet - Page 19

• Manufacturer Part Number: CY8C3246LTI-125
• Description: PSOC3
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C32xxr

Specifications of CY8C3246LTI-125

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART, USB
• Peripherals: CapSense, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Data Converters: A/D 2x12b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: CY8C32
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 31
• Number Of Timers: 4
• Operating Supply Voltage: 1.71 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document Number: 001-56955 Rev. *J
Notes
1: Interrupt triggered asynchronous to the clock
2: The PEND bit is set on next active clock edge to indicate the interrupt arrival
3: POST bit is set following the PEND bit
4: Interrupt request and the interrupt number sent to CPU core after evaluation priority (Takes 3 clocks)
5: ISR address is posted to CPU core for branching
6: CPU acknowledges the interrupt request
7: ISR address is read by CPU for branching
8, 9: PEND and POST bits are cleared respectively after receiving the IRA from core
10: IRA bit is cleared after completing the current instruction and starting the instruction execution from ISR location (Takes 7 cycles)
11: IRC is set to indicate the completion of ISR, Active int. status is restored with previous status
The total interrupt latency (ISR execution)
= 12 cycles
= POST + PEND + IRQ + IRA + Completing current instruction and branching
= 1+1+1+2+7 cycles
ACTIVE_INT_NUM
INT_VECT_ADDR
INT_INPUT
PEND
POST
(#10)
IRA
CLK
IRQ
IRC
1
Interrupt generation and posting to CPU
Arrival of new Interrupt
2
Pend bit is set on next system clock active edge
NA
NA
3
Interrupt is posted to ascertain the priority
4
Interrupt request sent to core for processing
5
CPU Response
address is posted to core
The active interrupt ISR
Figure 4-2. Interrupt Processing Timing Diagram
0x0010
6
Int. State
number is posted to core
Clear
The active interrupt
7
IRQ cleared after receiving IRA
8
Completing current instruction and branching to vector address
9
POST and PEND bits cleared after IRQ is sleared
NA
10
Complete ISR and return
PSoC
®
S
S
S
S
S
S
S
S
S
S
S
3: CY8C32 Family
11
0x0000
Data Sheet
Page 19 of 119
TIME
[+] Feedback