CY8C3246LTI-125 Cypress Semiconductor Corp, CY8C3246LTI-125 Datasheet - Page 50

• Manufacturer Part Number: CY8C3246LTI-125
• Description: PSOC3
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C32xxr

Specifications of CY8C3246LTI-125

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART, USB
• Peripherals: CapSense, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Data Converters: A/D 2x12b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: CY8C32
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 31
• Number Of Timers: 4
• Operating Supply Voltage: 1.71 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
CPU intervention. Additionally the device can wake from
low-power modes on a 7-bit hardware address match. If wakeup
functionality is required, I
two special sets of SIO pins.
I
Document Number: 001-56955 Rev. *J
2
2
SDA
SCL
C provides hardware address detect of a 7-bit address without
C features include:
Slave and Master, Transmitter, and Receiver operation
Byte processing for low CPU overhead
Interrupt or polling CPU interface
Support for bus speeds up to 1 Mbps (3.4 Mbps in UDBs)
7 or 10-bit addressing (10-bit addressing requires firmware
support)
Condition
START
ADDRESS
1 - 7
2
C pin connections are limited to the
R/W
8
Figure 7-20. I
ACK
9
2
1 - 7
C Complete Transfer Timing
DATA
Data transfers follow the format shown in
START condition (S), a slave address is sent. This address is 7
bits long followed by an eighth bit which is a data direction bit
(R/W) - a 'zero' indicates a transmission (WRITE), a 'one'
indicates a request for data (READ). A data transfer is always
terminated by a STOP condition (P) generated by the master.
However, if a master still wishes to communicate on the bus, it
can generate a repeated START condition (Sr) and address
another slave without first generating a STOP condition. Various
combinations of read/write formats are then possible within such
a transfer.
8
SMBus operation (through firmware support – SMBus
supported in hardware in UDBs)
7-bit hardware address compare
Wake from low-power modes on address match
ACK
9
PSoC
1 - 7
DATA
®
3: CY8C32 Family
8
Figure
ACK
Data Sheet
9
Page 50 of 119
7-20. After the
Condition
STOP
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