CY8C3665AXI-010 Cypress Semiconductor Corp, CY8C3665AXI-010 Datasheet
CY8C3665AXI-010
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CY8C3665AXI-010 Summary of contents
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... AHB – AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus 2. This feature on select devices only. See Ordering Information 3. GPIOs with opamp outputs are not recommended for use with CapSense. Cypress Semiconductor Corporation Document Number: 001-53413 Rev. *J PRELIMINARY ® ...
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Contents 1. ARCHITECTURAL OVERVIEW ......................................... 3 2. PINOUTS ............................................................................. 5 3. PIN DESCRIPTIONS ......................................................... 10 4. CPU ................................................................................... 11 4.1 8051 CPU ................................................................. 11 4.2 Addressing Modes .................................................... 11 4.3 Instruction Set .......................................................... 11 4.4 DMA and PHUB ....................................................... 15 ...
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Architectural Overview Introducing the CY8C36 family of ultra low-power, flash Programmable System-on-Chip (PSoC PSoC 3 and 32-bit PSoC 5 platform. The CY8C36 family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. The combination of ...
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In addition to the flexibility of the UDB array, PSoC also provides configurable digital blocks targeted at specific functions. For the CY8C36 family these blocks can include four 16-bit timers, 2 counters, and PWM blocks slave, master, and ...
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The CY8C36 family supports a wide supply operating range from 1.71 to 5.5 V. This allows operation from regulated supplies such as 1.8 ± 5%, 2.5 V ±10%, 3.3 V ± 10%, or 5.0 V ± 10%, or directly from ...
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P2[6] (GPIO) P2[7] (GPIO, TMS, SWDIO) P1[0] (GPIO, TCK, SWDCK) P1[1] (GPIO, Configurable XRES) P1[2] (GPIO, TDO, SWV) P1[3] (GPIO, TDI) P1[4] (GPIO, nTRST) P1[5] Notes 6. Pins are Do Not Use (DNU) on devices without USB. The pin ...
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P2[6] (GPIO) P2[7] (I2C0: SCL, SIO) P12[4] (I2C0: SDA, SIO) P12[5] Vssb Vboost Vssd XRES (TMS, SWDIO, GPIO) P1[0] (TCK, SWDCK, GPIO) P1[1] (configurable XRES, GPIO) P1[2] (TDO, SWV, GPIO) P1[3] (TDI, GPIO) P1[4] (nTRST, GPIO) P1[5] Vddio1 Notes ...
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P2[5] (GPIO) P2[6] (GPIO) P2[7] (I2C0: SCL, SIO) P12[4] (I2C0: SDA, SIO) P12[5] (GPIO) P6[4] (GPIO) P6[5] (GPIO) P6[6] (GPIO) P6[7] Vssb Ind Vboost Vbat Vssd XRES (GPIO) P5[0] (GPIO) P5[1] (GPIO) P5[2] (GPIO) P5[3] (TMS, SWDIO, GPIO) P1[0] ...
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Figure 2-5. Example Schematic for 100-pin TQFP Part With Power Connections Vddd C6 0.1 uF Vssd 1 P2[5] 2 P2[6] 3 P2[7] 4 P12[4], SIO 5 P12[5], SIO 6 P6[4] 7 P6[5] 8 P6[6] 9 P6[7] 10 Vssb 11 Ind ...
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Figure 2-6. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance Vssd Plane 3. Pin Descriptions IDAC0, IDAC1, IDAC2, IDAC3. Low resistance output pin for high current DACs (IDAC). [15] OpAmp0out, OpAmp1out , OpAmp2out, OpAmp3out High current output ...
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Vccd. Output of digital core regulator and input to digital core. The two Vccd pins must be shorted together, with the trace between them as short as possible, and a 1-µF capacitor to Vssd; see Power System on page 24. ...
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Table 4-1. Arithmetic Instructions Mnemonic ADD A,Rn Add register to accumulator ADD A,Direct Add direct byte to accumulator ADD A,@Ri Add indirect RAM to accumulator ADD A,#data Add immediate data to accumulator ADDC A,Rn Add register to accumulator with carry ...
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Table 4-2. Logical Instructions (continued) Mnemonic ORL A,#data OR immediate data to accumulator ORL Direct accumulator to direct byte ORL Direct, #data OR immediate data to direct byte XRL A,Rn XOR register to accumulator XRL A,Direct XOR direct ...
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Table 4-3. Data Transfer Instructions (continued) Mnemonic MOV @Ri, Direct Move direct byte to indirect RAM MOV @Ri, #data Move immediate data to indirect RAM MOV DPTR, #data16 Load data pointer with 16 bit constant MOVC A, @A+DPTR Move code ...
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Program Branching Instructions The 8051 supports a set of conditional and unconditional jump instructions that help to modify the program execution flow. shows the list of jump instructions. Table 4-5. Jump Instructions Mnemonic ACALL addr11 Absolute subroutine call LCALL ...
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Priority Levels The CPU always has higher priority than the DMA controller when their accesses require the same bus resources. Due to the system architecture, the CPU can never starve the DMA. DMA channels of higher priority (lower priority ...
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Interrupt Controller The interrupt controller provides a mechanism for hardware resources to change program execution to a new address, independent of the current task being executed by the main code. The interrupt controller provides enhanced features not found on ...
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Memory 5.1 Static RAM CY8C36 Static RAM (SRAM) is used for temporary data storage SRAM is provided and can be accessed by the 8051 or the DMA controller. See Memory Map Simultaneous access of ...
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Data, Address, and Control Signals PHUB Data, Address, and Control Signals Data, Address, and Control Signals 5.6 Memory Map The CY8C36 8051 memory map is very similar to the MCS-51 memory map. 5.6.1 Code Space The CY8C36 8051 code space ...
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SFRs The special function register (SFR) space provides access to frequently accessed registers. The memory map for the SFR memory space is shown in Table 5-2. Table 5-2. SFR Map Address 0/8 1/9 0×F8 SFRPRT15DR SFRPRT15PS 0×F0 B – ...
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Space The 8051 xdata space is 24-bit size. The majority of this space is not “external”—it is used by on-chip components. See Table 5-3. External, that is, off-chip, memory can be accessed using the ...
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MHz 4-33 MHz IMO ECO 12-48 MHz Doubler Digital Clock Divider 16 bit Digital Clock Divider 16 bit 7 Digital Clock Divider 16 bit Digital Clock Divider 16 bit Table 6-1. Oscillator Summary Source Fmin Tolerance at Fmin IMO ...
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The PLL block provides a mechanism for generating clock frequencies based upon a variety of input sources. The PLL outputs clock frequencies in the range MHz. Its input and feedback dividers supply 4032 discrete ratios to ...
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Clock Distribution All seven clock sources are inputs to the central clock distribution system. The distribution system is designed to create multiple high precision clocks. These clocks are customized for the design’s requirements and eliminate the common problems found ...
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Power Modes PSoC 3 devices have four different power modes, as shown in Table 6-1 and Table 6-2. The power modes allow a design to easily provide required functionality and processing power while simultaneously minimizing power consumption and maximizing ...
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Figure 6-5. Power Mode Transitions Active Manual Sleep Hibernate Alternate Active 6.2.1.1 Active Mode Active mode is the primary operating mode of the device. When in active mode, the active configuration template bits control which available resources are enabled or ...
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In standby mode, most boost functions are disabled, thus reducing power consumption of the boost circuit. The converter can be configured to provide low-power, low-current regulation in the standby mode. ...
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ALVI, DLVI, AHVI – Analog/Digital Low Voltage Interrupt, Analog High Voltage Interrupt Interrupt circuits are available to detect when Vdda and Vddd go outside a voltage range. For AHVI, Vdda is compared to a fixed trip level. For ALVI and ...
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Digital Input Path PRT[x]CTL PRT[x]DBL_SYNC_IN PRT[x]PS Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Pin Interrupt Signal PICU[x]INTSTAT Digital Output Path PRT[x]SLW PRT[x]SYNC_OUT PRT[x]DR Digital System Output PRT[x]BYP PRT[x]DM2 PRT[x]DM1 PRT[x]DM0 Bidirectional Control PRT[x]BIE Analog Capsense Global Control CAPS[x]CFG1 PRT[x]AG Analog Global Enable ...
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Digital Input Path PRT[x]SIO_HYST_EN PRT[x]SIO_DIFF Reference Level PRT[x]DBL_SYNC_IN PRT[x]PS Digital System Input PICU[x]INTTYPE[y] PICU[x]INTSTAT Pin Interrupt Signal PICU[x]INTSTAT Digital Output Path Reference Level PRT[x]SIO_CFG PRT[x]SLW PRT[x]SYNC_OUT PRT[x]DR Digital System Output PRT[x]BYP PRT[x]DM2 PRT[x]DM1 PRT[x]DM0 Bidirectional Control PRT[x]BIE Digital Input Path ...
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Drive Modes Each GPIO and SIO pin is individually configurable into one of the eight drive modes listed in used for each pin (DM[2:0]) and set in the PRTxDM[2:0] registers. drive modes. Table 6-3 shows the I/O pin’s drive ...
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High Impedance Analog The default reset state with both the output driver and digital input buffer turned off. This prevents any current from flowing in the I/O’s digital input buffer due to a floating voltage. This state is recommended for ...
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ADC or comparators. In addition, select pins provide direct connections to specific analog features such as the high current ...
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Over Voltage Tolerance All I/O pins provide an over voltage tolerance feature at any operating There are no current limitations for the SIO pins as they present a high impedance load to the external circuit where ...
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Example Peripherals The flexibility of the CY8C36 family’s Universal Digital Blocks (UDBs) and Analog Blocks allow the user to create a wide range of components (peripherals). The most common peripherals were built and characterized by Cypress and are shown ...
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Document Number: 001-53413 Rev. *J PRELIMINARY ® PSoC 3: CY8C36 Family Datasheet Figure 7-2. PSoC Creator Framework Page 36 of 111 [+] Feedback [+] Feedback ...
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Component Catalog Figure 7-3. Component Catalog The component catalog is a repository of reusable design elements that select device functionality and customize your PSoC device populated with an impressive selection of content; from simple primitives such as ...
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PSoC Creator contains all the tools necessary to complete a design, and then to maintain and extend that design for years to come. All steps of the design flow are carefully integrated and optimized for ease-of-use and to maximize productivity. ...
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Datapath Module The datapath contains an 8-bit single cycle ALU, with associated compare and condition generation logic. This datapath block is optimized to implement embedded functions, such as timers, counters, integrators, PWMs, PRS, CRC, shifters and dead band generators ...
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Independent of the ALU operation, these functions are available: Shift left Shift right Nibble swap Bitwise OR mask 7.2.2.3 Conditionals Each datapath has two compares, with bit masking options. Compare operands include the two accumulators and the two data registers ...
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UDB Array Description Figure 7-11 shows an example of a 16-UDB array. In addition to the array core, there are a DSI routing interfaces at the top and bottom of the array. Other interfaces that are not explicitly shown ...
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Figure 7-13. Digital System Interconnect Timer Interrupt DMA CAN I2C Counters Controller Controller Digital System Routing I/F UDB ARRAY Digital System Routing I/F Global IO Port SC/CT EMIF Del-Sig Clocks Pins Blocks Interrupt and DMA routing is very flexible in ...
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Figure 7-17. I/O Pin Output Enable Connectivity 4 IO Control Signal Connections from UDB Array Digital System Interface PIN 0 PIN1 PIN2 PIN3 PIN4 PIN5 Port i CAN Node 1 PSoC CAN Drivers CAN ...
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Tx Buffer Status TxReq Pending TxInterrupt Request (if enabled) Acceptance Code 0 Rx Buffer RxMessage0 Status RxMessage RxMessage1 Acceptance Code 1 Available RxMessage14 Acceptance Code 14 RxInterrupt RxMessage15 Acceptance Code 15 Request (if enabled) 7.6 USB PSoC includes a dedicated ...
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Timers, Counters, and PWMs The Timer/Counter/PWM peripheral is a 16-bit dedicated peripheral providing three of the most common embedded peripheral features. As almost all embedded systems use some combination of timers, counters, and PWMs. Four of them have been ...
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Figure 7-22. DFB Application Diagram (pwr/gnd not shown) BUSCLK read_data write_data System Bus addr Digital Digital Filter Routing Block DMA Request DMA CTRL The typical use model is for data to be supplied to the DFB over the system bus ...
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The PSoC Creator software program provides a user friendly interface to configure the analog connections between the GPIO and various analog resources and connections from one analog resource to another. PSoC Creator also provides component libraries that allow you to ...
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ExVrefL ExVrefL1 opamp0 opamp2 swinp GPIO swfol swfol P0[4] swinn GPIO P0[5] GPIO * i0 abuf_vref_int P0[6] (1.024V) GPIO * i2 P0[7] cmp0_vref (1.024V) GPIO cmp_muxvn[1:0] vref_cmp1 P4[2] cmp1_vref (0.256V) GPIO bg_vda_res_en Vdda Vdda/2 ...
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Analog local buses (abus) are routing resources located within the analog subsystem and are used to route signals between different analog blocks. There are eight abus routes in CY8C36, four in the left half (abusl [0:3]) and four in the ...
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The ADC result is valid and available after the fourth conversion, at which time the EoC signal is generated. To detect the end of conversion, the system may poll a control register for status ...
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LUT The CY8C36 family of devices contains four LUTs. The LUT is a two input, one output lookup table that is driven by any one or two of the comparators in the chip. The output of any LUT is ...
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The same opamps and block interfaces are also connectable to an array of resistors which allows the construction of a variety of continuous time functions. The opamp and resistor array is programmable to perform various analog functions including Naked operational ...
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PSoC Creator provides an LCD segment drive component. The component wizard provides easy and flexible configuration of LCD resources. You can specify pins for segments and commons along with other options. The software configures the device to meet the required ...
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Reference Source 8.9.1 Current DAC The current DAC (IDAC) can be configured for the ranges µ 256 µA, and 0 to 2.048 mA. The IDAC can be configured to source or sink current. 8.9.2 Voltage ...
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Down Mixer The SC/CT block can be used as a mixer to down convert an input signal. This circuit is a high bandwidth passive sample network that can sample input signals MHz. This sampled value is ...
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One memory access breakpoint—break on reading or writing any memory address and data value Break on a sequence of breakpoints (non recursive) Debugging at the full speed of the CPU Debug operations are possible while the device is reset, or ...
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Development Support The CY8C36 family has a rich set of documentation, development tools, and online resources to assist you during your development process. Visit psoc.cypress.com/getting-started to find out more. 10.1 Documentation A suite of documentation, supports the CY8C36 family ...
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Electrical Specifications Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC Creator components, ...
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Device Level Specifications Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.2.1 Device Level Specifications Table 11-2. DC Specifications Parameter Description V Analog supply voltage and input to DDA analog ...
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Table 11-2. DC Specifications (continued) Parameter Description [26] Sleep Mode CPU = OFF RTC = ON (= ECO32K ON, in low-power mode) Sleep timer = ON (= ILO ON at [27] 1 kHz) WDT = OFF Wake ...
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Table 11-3. AC Specifications Parameter Description F CPU frequency CPU F Bus frequency BUSCLK Svdd V ramp rate DD T Time from IO_INIT DDD DDA ≥ IPOR to I/O ports set to their reset states T ...
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Power Regulators Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.3.1 Digital Core Regulator Table 11-4. Digital Core Regulator DC Specifications Parameter Description V Input voltage DDD V Output voltage ...
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Table 11-6. Inductive Boost Regulator DC Specifications (continued) Unless otherwise specified, operating conditions are µF || 0.1 µF BOOST Parameter Description V [31, 32] OUT Boost voltage range 1.8 V 1.9 V 2.0 V 2.4 V ...
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Inputs and Outputs Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.4.1 GPIO Table 11-9. GPIO DC Specifications Parameter Description V Input voltage high threshold IH V Input voltage low ...
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SIO Table 11-11. SIO DC Specifications Parameter Description Vinmax Maximum input voltage Vinref Input voltage reference (Differ- ential input mode) Output voltage reference (Regulated output mode) Voutref Input voltage high threshold V GPIO mode IH [34] Differential input mode ...
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Table 11-12. SIO AC Specifications (continued) Parameter Description SIO output operating frequency 3.3 V < V < 5.5 V, Unregu- DDIO lated output (GPIO) mode, fast strong drive mode 1.71 V < V < 3.3 V, Unregu- DDIO lated output ...
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Table 11-14. USBIO AC Specifications Parameter Description Tdrate Full-speed data rate average bit rate Tjr1 Receiver data jitter tolerance to next transition Tjr2 Receiver data jitter tolerance to pair transition Tdj1 Driver differential jitter to next transition Tdj2 Driver differential ...
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Analog Peripherals Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.5.1 Opamp Table 11-18. Opamp DC Specifications Parameter Description V Input offset voltage IOFF Vos Input offset voltage TCVos Input ...
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Figure 11-11. Opamp Voffset vs Common Mode Voltage and Temperature, Power Mode = High Figure 11-13. Opamp Operating Current vs Vdda, Power Mode = Minimum Figure 11-15. Opamp Operating Current vs Vdda, Power Mode = Medium Document Number: 001-53413 Rev. ...
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Table 11-19. Opamp AC Specifications Parameter Description GBW Gain-bandwidth product SR Slew rate, 20% - 80% e Input noise density n Figure 11-17. Open Loop Gain and Phase vs Frequency and Temperature, Power Mode = High Pf, ...
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Figure 11-21. Opamp Noise vs Frequency, Power Mode = High, Vdda = 5V Figure 11-23. Opamp PSRR vs Frequency Note 37. Based on device characterization (Not production tested). Document Number: 001-53413 Rev. *J PRELIMINARY ® PSoC 3: CY8C36 Family Datasheet ...
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Delta-Sigma ADC Unless otherwise specified, operating conditions are: Operation in continuous sample mode fclk = 6.144 MHz Reference = 1.024 V internal reference bypassed on P3.2 or P0.3 Unless otherwise specified, all charts and graphs show typical values Table ...
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Table 11-21. Delta-sigma ADC AC Specifications Parameter Description Startup time [40] THD Total harmonic distortion 12-Bit Resolution Mode SR12 Sample rate, continuous, high power BW12 Input bandwidth at max sample rate SINAD12int Signal to noise ratio, 12-bit, internal reference 8-Bit ...
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Figure 11-26. Delta-sigma ADC Noise Histogram, 1000 sam- ples, 12-bit, 192 ksps, Int Ref REF 100.00 90.00 80.00 70.00 60.00 50.00 40.00 30.00 20.00 10.00 0.00 ADC counts ADC Counts 11.5.3 Voltage Reference Table 11-23. Voltage ...
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Comparator Table 11-25. Comparator DC Specifications Parameter Description Input offset voltage in fast mode V OS Input offset voltage in slow mode Input offset voltage in fast mode V OS Input offset voltage in slow mode V Input offset ...
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Table 11-27. IDAC DC Specifications (continued) Parameter Description Eg Gain error TC_Eg Temperature coefficient of gain error INL Integral nonlinearity DNL Differential nonlinearity Vcompliance Dropout voltage, source or sink mode I Operating current, code = 0 DD Document Number: 001-53413 ...
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Figure 11-27. IDAC INL vs Input Code, Range = 255 µA, Source Mode Figure 11-29. IDAC DNL vs Input Code, Range = 255 µA, Source Mode Figure 11-31. IDAC INL vs Temperature, Range = 255 µA, Fast Mode Document Number: ...
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Figure 11-33. IDAC Full Scale Error vs Temperature, Range = 255 µA, Source Mode Figure 11-35. IDAC Operating Current vs Temperature, Range = 255 µA, Code = 0, Source Mode Table 11-28. IDAC AC Specifications Parameter Description F Update rate ...
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Voltage Digital to Analog Converter (VDAC) See the VDAC component datasheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, all charts and graphs show typical values. Table 11-29. VDAC DC Specifications Parameter Description Resolution INL1 ...
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Figure 11-41. VDAC Full Scale Error vs Temperature Mode Figure 11-43. VDAC Operating Current vs Temperature, 1V Mode, Slow Mode Table 11-30. VDAC AC Specifications Parameter Description F Update rate DAC TsettleP Settling time to 0.1%, step 25% ...
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Mixer The mixer is created using a SC/CT analog block; see the Mixer component datasheet in PSoC Creator for full electrical specifications and APIs. Table 11-31. Mixer DC Specifications Parameter Description V Input offset voltage OS Quiescent current G ...
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Programmable Gain Amplifier The PGA is created using a SC/CT analog block; see the PGA component datasheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, operating conditions are: Operating temperature = 25 °C for typical ...
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Table 11-36. PGA AC Specifications Parameter Description BW1 –3 dB bandwidth SR1 Slew rate e Input noise density n Figure 11-46. Gain vs. Frequency, at Different Gain Settings, Vdda = 3.3 V, Power Mode = High Figure 11-48. Noise vs. ...
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LCD Direct Drive Table 11-38. LCD Direct Drive DC Specifications Parameter Description I LCD system operating current CC I Current per segment driver CC_SEG V LCD bias range (V refers to the BIAS BIAS main output voltage(V0) of LCD ...
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Digital Peripherals Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.6.1 Timer The following specifications apply to the Timer/Counter/PWM peripheral in timer mode. Timers can also be implemented in UDBs; ...
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Pulse Width Modulation The following specifications apply to the Timer/Counter/PWM peripheral, in PWM mode. PWM components can also be implemented in UDBs; for more information, see the PWM component datasheet in PSoC Creator. Table 11-44. PWM DC Specifications Parameter ...
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Digital Filter Block Table 11-49. DFB DC Specifications Parameter Description DFB operating current Table 11-50. DFB AC Specifications Parameter Description F DFB operating frequency DFB 11.6.7 USB Table 11-51. USB DC Specifications Parameter Description V Device supply for USB ...
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Universal Digital Blocks (UDBs) PSoC Creator provides a library of prebuilt and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM, AND, OR, and so on) that are mapped to the UDB array. See the component ...
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Table 11-54. Flash AC Specifications Parameter Description T Row write time (erase + program) WRITE T Row erase time ERASE Row program time T Bulk erase time ( KB) BULK Sector erase time ( ...
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External Memory Interface Figure 11-50. Asynchronous Read Cycle Timing EM_ CEn Taddrv EM_ Addr EM_ OEn EM_ WEn EM_ Data Table 11-61. Asynchronous Read Cycle Specifications Parameter Description [48] T EMIF clock period Tcel EM_CEn low time Taddrv EM_CEn ...
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Figure 11-51. Asynchronous Write Cycle Timing Taddrv EM_ Addr EM_ CEn EM_ WEn EM_ OEn Tdcev EM_ Data Table 11-62. Asynchronous Write Cycle Specifications Parameter Description [49] T EMIF clock period Tcel EM_CEn low time Taddrv EM_CEn low to EM_Addr ...
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EM_ Clock EM_ CEn EM_ Addr EM_ OEn EM_ Data EM_ ADSCn Table 11-63. Synchronous Read Cycle Specifications Parameter Description [50] T EMIF clock period Tcp/2 EM_Clock pulse high Tceld EM_CEn low to EM_Clock high Tcehd EM_Clock high to EM_CEn ...
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EM_ Clock EM_ CEn EM_ Addr EM_ WEn EM_ Data EM_ ADSCn Table 11-64. Synchronous Write Cycle Specifications Parameter Description [51] T EMIF clock Period Tcp/2 EM_Clock pulse high Tceld EM_CEn low to EM_Clock high Tcehd EM_Clock high to EM_CEn ...
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PSoC System Resources Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.8.1 POR with Brown Out For brown out detect in regulated mode, V mode. Table 11-65. Precise Power On ...
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Interrupt Controller Table 11-69. Interrupt Controller AC Specifications Parameter Description Delay from interrupt signal input to ISR code execution from ISR code 11.8.4 JTAG Interface Table 11-70. JTAG Interface AC Specifications Parameter Description f_TCK TCK frequency T_TDI_setup TDI setup ...
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Clocking Specifications are valid for –40 °C ≤ T ≤ 85 °C and T A except where noted. 11.9.1 32 kHz External Crystal Table 11-73. 32 kHz External Crystal DC Specifications Parameter Description I Operating current CC CL External ...
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Table 11-76. IMO AC Specifications (continued) Parameter Description [56] Jitter (peak to peak) Jp– MHz MHz [56] Jitter (long term) Jperiod MHz MHz 11.9.3 Internal Low Speed Oscillator ...
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Phase-Locked Loop Table 11-81. PLL DC Specifications Parameter Description I PLL operating current DD Table 11-82. PLL AC Specifications Parameter Description [57] Fpllin PLL input frequency PLL intermediate frequency [57] Fpllout PLL output frequency Lock time at startup [59] ...
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... PSoC Creator makes a part recommendation after you choose the components required by your application. All CY8C36 derivatives incorporate device and flash security in user-selectable security levels; see the TRM for details. Table 12-1. CY8C36 Family with Single Cycle 8051 MCU Core Part Number 32 KB Flash CY8C3665AXI-010 – ...
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Table 12-1. CY8C36 Family with Single Cycle 8051 (continued) MCU Core Part Number ✔ 12-bit Del-Sig CY8C3666LTI-012 CY8C3666PVI-026 ✔ 12-bit Del-Sig CY8C3666AXI-036 ✔ 12-bit Del-Sig CY8C3666LTI-027 67 64 ...
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Part Numbering Conventions PSoC 3 devices follow the part numbering convention described here. All fields are single character alphanumeric ( … …, Z) unless stated otherwise. CY8Cabcdefg-xxx a: Architecture 3: PSoC 3 5: PSoC ...
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Packaging Table 13-1. Package Characteristics Parameter Description T Operating ambient temperature A T Operating junction temperature J Package θJA (48-pin SSOP) Tja Package θJA (48-pin QFN) Tja Package θJA (68-pin QFN) Tja Package θJA (100-pin TQFP) Tja Package θJC ...
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TOP VIEW 7.00±0. PIN 1 DOT LASER MARK NOTES: 1. HATCH AREA IS SOLDERABLE EXPOSED METAL. 2. REFERENCE JEDEC#: MO-220 3. PACKAGE WEIGHT: 0.13g 4. ALL DIMENSIONS ARE IN MM [MIN/MAX] 5. PACKAGE CODE ...
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Figure 13-4. 100-pin TQFP (14 × 14 × 1.4 mm) Package Outline Document Number: 001-53413 Rev. *J PRELIMINARY ® PSoC 3: CY8C36 Family Datasheet 51-85048 *E Page 104 of 111 [+] Feedback [+] Feedback ...
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Acronyms Table 14-1. Acronyms Used in this Document Acronym Description abus analog local bus ADC analog-to-digital converter AG analog global AHB AMBA (advanced microcontroller bus archi- tecture) high-performance bus, an ARM data transfer bus ALU arithmetic logic unit AMUXBUS ...
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Table 14-1. Acronyms Used in this Document (continued) Acronym Description PGA programmable gain amplifier PHUB peripheral hub PHY physical layer PICU port interrupt control unit PLA programmable logic array PLD programmable logic device, see also PAL PLL phase-locked loop PMDD ...
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Document Conventions 16.1 Units of Measure Table 16-1. Units of Measure Symbol Unit of Measure °C degrees Celsius dB decibels fF femtofarads Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohours kHz kilohertz kΩ kilohms ksps kilosamples ...
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Revision History ® Description Title: PSoC 3: CY8C36 Family Datasheet Programmable System-on-Chip (PSoC Document Number: 001-53413 Submission Rev. ECN No. Date ** 2714854 06/04/09 *A 2758970 09/02/09 *B 2824546 12/09/09 *C 2873322 02/04/10 Document Number: 001-53413 Rev. *J PRELIMINARY ...
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Description Title: PSoC 3: CY8C36 Family Datasheet Programmable System-on-Chip (PSoC Document Number: 001-53413 *D 2903576 04/01/10 Document Number: 001-53413 Rev. *J PRELIMINARY ® PSoC MKEA Updated Vb pin in PCB Schematic Updated Tstartup parameter in AC Specifications table Added ...
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Description Title: PSoC 3: CY8C36 Family Datasheet Programmable System-on-Chip (PSoC Document Number: 001-53413 *E 2938381 05/27/10 *F 2958674 06/22/10 *G 2989685 08/04/10 *H 3078568 11/04/10 *I 3107314 12/10/2010 *J 3179219 02/22/2011 Document Number: 001-53413 Rev. *J PRELIMINARY ® PSoC ...
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... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...