CY8C3665AXI-010 Cypress Semiconductor Corp, CY8C3665AXI-010 Datasheet - Page 93

• Manufacturer Part Number: CY8C3665AXI-010
• Description: PSOC3
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C36xxr

Specifications of CY8C3665AXI-010

• Package / Case: *
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 67MHz
• Number Of I /o: 62
• Eeprom Size: 1K x 8
• Core Processor: 8051
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 32KB (32K x 8)
• Data Converters: A/D 2x12b, D/A 4x8b
• Oscillator Type: Internal
• Peripherals: CapSense, DMA, POR, PWM, WDT
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Technology: CMOS
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Package Type: TQFP
• Screening Level: Industrial
• Pin Count: 100
• Mounting: Surface Mount
• Rad Hardened: No
• Processor Series: CY8C36
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 67 MHz
• Number Of Programmable I/os: 28 to 72
• Number Of Timers: 4
• Operating Supply Voltage: 0.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 62
• Eeprom Memory Size: 1KB
• Ram Memory Size: 4KB
• Cpu Speed: 67MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 11-64. Synchronous Write Cycle Specifications
Document Number: 001-53413 Rev. *J
Note
T
Tcp/2
Tceld
Tcehd
Taddrv
Taddriv
Tweld
Twehd
Tds
Tdh
Tadscld
Tadschd
Parameter
51. Limited by GPIO output frequency, see
EMIF clock Period
EM_Clock pulse high
EM_CEn low to EM_Clock high
EM_Clock high to EM_CEn high
EM_Addr valid to EM_Clock high
EM_Clock high to EM_Addr invalid
EM_WEn low to EM_Clock high
EM_Clock high to EM_WEn high
Data valid before EM_Clock high
Data invalid after EM_Clock high
EM_ADSCn low to EM_Clock high
EM_Clock high to EM_ADSCn high
EM_ ADSCn
EM_ Data
EM_ Clock
EM_ Addr
EM_ WEn
EM_ CEn
Description
[51]
Table 11-10
Figure 11-53. Synchronous Write Cycle Timing
Tds
Tceld
Tweld
Taddrv
Tadscld
on page 64.
PRELIMINARY
Vdda ≥ 3.3 V
Tcp/2
Address
Data
Conditions
Tcehd
Twehd
Tadschd
Tdh
PSoC
®
3: CY8C36 Family Datasheet
Taddriv
T/2 – 5
T/2 – 5
T/2 – 5
T/2 – 5
30.3
Min
T/2
T
5
5
5
5
5
Typ
–
–
–
–
–
–
–
–
–
–
–
–
Max
–
–
–
–
–
–
–
–
–
–
–
–
Page 93 of 111
Units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
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