DSPIC33FJ06GS202T-I/SO Microchip Technology, DSPIC33FJ06GS202T-I/SO Datasheet - Page 2

• Manufacturer Part Number: DSPIC33FJ06GS202T-I/SO
• Description: 16 Bit MCU/DSP 40MIPS 6 KB FLASH 1 KB RAM SMPS 28 SOIC .300in T/R
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ06GS202T-I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 2:
DS80439H-page 2
Note 1:
Comparator
Comparator
Auxiliary
Module
UART
UART
PWM
PWM
PWM
PWM
Clock
I
PWM
PWM
PWM
PWM
PWM
PWM
ADC
2
C™
Only those issues indicated in the last column apply to the current silicon revision.
Module Disable
SILICON ISSUE SUMMARY
Latched Faults
Leading-Edge
Independent
Sleep Mode
IR Interface
Conversion
Addressing
Operations
Immediate
Status Bits
Time Base
Interrupts
Blanking
Updates
4x Mode
Feature
Faults
Faults
Clock
Clock
10-bit
Mode
ADC
—
Number
Item
10.
12.
13.
14.
15.
16.
17.
11.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Reading LEBCONx registers, as well as writing individual
bits and bytes within these registers, does not work.
PWM Immediate Update mode (IEU = 1) for the Master
Duty Cycle register (MDC) is not functional.
PWM Fault Status bits do not function if the associated
PWM Fault interrupts are disabled.
PWM output will exhibit jitter with some PWM clock divider
settings.
If the PWM is in Complementary, Redundant and Push-
Pull mode and the Independent Time Base bit (ITB) is set,
the Independent Fault mode may not work as expected for
the PWMxL pin.
The independent time base PWM outputs may not be
synchronized with the Master time base PWM outputs
when both modes are used simultaneously.
In PWM Latched Fault mode, the PWM outputs may be
latched on both the rising as well as the falling edge of the
Fault signal regardless of the fault input polarity selection
(set with the FCLCONx<FLTPOL> bit setting).
A bit write to the CLMOD bit (bit 8) in the FCLCONx
register, or consecutive writes to the lower byte and higher
byte of the FCLCONx register, causes all other bits of the
high byte to be loaded with zeros.
The PWM module fails to wake the CPU from Sleep mode
on a PWM fault event.
For slow input signals, the Comparator module may
generate erroneous triggers/interrupts.
Selecting the primary FRC (F
the ADC module by setting the SLOWCLK bit
(ADCON<12>) to the default setting of ‘0’, does not work.
When the PWMMD bit in the PMD1 register is set, the
Auxiliary Clock to both the ADC and PWM modules is
disabled.
Comparator interrupts are incorrectly generated when the
High-Speed Analog Comparator is configured for an
inverted polarity setting (CMPCONx<CMPPOL> = 1).
When the UART is in 4x mode (BRGH = 1) and using two
Stop bits (STSEL = 1), it may sample the first Stop bit
instead of the second one.
The 16x baud clock signal on the BCLK pin is present only
when the module is transmitting.
When the I
using the same address bits (A10 and A9) as other I
devices, the A10 and A9 bits may not work as expected.
The PWM module may fail to trigger a conversion on
certain ADC pairs when the primary or secondary PWMx
generator is selected as a trigger source.
2
C module is configured for 10-bit addressing
Issue Summary
VCO
) as a clock source for
© 2010 Microchip Technology Inc.
2
C
A2
Revisions
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Affected
A3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A4
(1)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X