DSPIC33FJ06GS202T-I/SO Microchip Technology, DSPIC33FJ06GS202T-I/SO Datasheet - Page 5

• Manufacturer Part Number: DSPIC33FJ06GS202T-I/SO
• Description: 16 Bit MCU/DSP 40MIPS 6 KB FLASH 1 KB RAM SMPS 28 SOIC .300in T/R
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ06GS202T-I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Silicon Errata Issues
1. Module: PWM
2. Module: PWM
© 2010 Microchip Technology Inc.
Note:
Reading LEBCONx registers, as well as writing
individual bits and bytes within these registers
does not work.
Work around
Use a Word write operation to modify LEBCONx
registers. For example, to set the PHR bit within
the LEBCON1 register, use the following C code:
LEBCON1 = 0x8000
There is no work around for reading LEBCONx
registers.
Affected Silicon Revisions
If PWM Immediate Update mode is selected
(IUE = 1), and the PWM duty cycle is provided via
the Master Duty Cycle (MDC) register (MDCS = 1
mode), the updates to the MDC register are
synchronized to the PWM time base instead of an
immediate update (duty cycle will be updated on
the next PWM period).
Work arounds
Work around 1:
Use the Enable Immediate Period Update mode
(EIPU = 1) in conjunction with PWM Immediate
Update mode (IUE = 1). This will update the period
and duty cycle on an immediate basis.
Work around 2:
Use individual duty cycle registers (PDCx) and
PWM Immediate Update mode (IUE = 1) to update
individual duty cycle registers on an immediate
basis.
Affected Silicon Revisions
A2
A2
X
X
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A4).
A3
A3
X
X
A4
A4
X
X
3. Module: PWM
4. Module: PWM
If PWM fault interrupts are disabled (FLTIEN = 0 or
CLIEN = 0), then associated Status bits (FLTSTAT
and CLSTAT) will not function.
Work around
Enable
CLIEN = 1).
Affected Silicon Revisions
The PWM output will exhibit jitter under the
following conditions:
When the PWM clock divider has the value of 1, 5
or 6 (PTCON2<PCLKDIV> = 0b001, 0b101 or
0b110), and the three Least Significant bits of the
PWM Period Register (PTPER or PHASEx), Duty
Cycle Register (MDC or PDCx) or Phase Register
(PHASEx) are non-zero.
Work around
Use PWM clock dividers other than 1, 5 or 6.
Affected Silicon Revisions
A2
A2
X
X
A3
A3
X
X
PWM
A4
A4
X
X
fault
interrupts
DS80439H-page 5
(FLTIEN = 1,