DSPIC33FJ128GP706A-E/MR Microchip Technology, DSPIC33FJ128GP706A-E/MR Datasheet - Page 32

• Manufacturer Part Number: DSPIC33FJ128GP706A-E/MR
• Description: 16 Bit MCU/DSP 40MIPS 128KB FLASH 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP706A-E/MR

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-VFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MCP3909 / dsPIC33F 3-Phase Energy Meter Reference Design
DS51723A-page 32
3.3.6
Energy accumulation is done by calculating the total energy, which is the algebraic sum
of energy of each phase. Active energy is obtained by accumulating the multiplication
of voltage and current of each sample, which ensures the high accuracy of measure-
ment.
3.3.7
The required measurement accuracy of reactive energy low, so in this design, it is
obtained by accumulating the product of the present measured reactive power and the
time interval between two measurements.
3.3.8
Refer to Section 2.4.2 “Energy Pulse Output Interface” for pulse output. To ensure
the uniformity of output pulses, the calculation is divided in the measurement cycle into
in a number of equal sections, and accumulate them. For simplification and lowering
computation complexity, a counter is used to substitute the process of accumulation.
The counter is only enabled when accumulated energy approaches to the threshold of
the pulse output.
3.3.9
Frequency calculation is based on Equation C-52 and Equation C-53, in Appendix
C. “Power Calculation Theory”. The dsPIC33F collects 3-line cycles worth of data.
The first two cycles of data of all sampled data is analyzed, and then the frequency of
two successive cycles is used.
The data of two successive cycles are transformed via DFT for the fundamental, which
is accomplished by assemble function DFT_Fundamental(). This is followed by the
computation of the initial phase angle of the first two line cycles. Then the phase lag
and frequency offset of the two line cycles of signal can be calculated.
When measuring frequency, only the first two cycles of data are used. It must be
assumed the input frequency is 50 Hz and the chosen appropriate sine/cosine table to
carry out DFT transform for fundamentals of the 1st and 2nd cycles of data. See
Appendix D. “50/60 Hz Meter Operation” for 60 Hz firmware.
Frequency offset is calculated by determining the initial phase angle for each line cycle.
The greater the frequency offset, the greater the measurement error.
Since one of the 3 phases may be missing, if the voltage magnitude for phase A is less
than the threshold, it is necessary to switch to phase B. Consequently, if sufficient volt-
age magnitude of phase B is not detected, it is necessary to switch to phase C.
The basic algorithm for measuring line frequency is based on the method described in
Appendix A, Section C.4 “Measuring The Voltage/current Rms Value And Power
Using Quasi-synchronous Sampling Algorithm”.
Frequency will be measured once for every 3 times the data is sampled.
Active Energy Accumulation
Reactive Energy Accumulation
Output Pulse Generation
Line Frequency Calculation
© 2009 Microchip Technology Inc.