DSPIC33FJ16MC304T-I/ML Microchip Technology, DSPIC33FJ16MC304T-I/ML Datasheet - Page 25

• Manufacturer Part Number: DSPIC33FJ16MC304T-I/ML
• Description: 16-bit DSC, 16KB Flash,Motor,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm T/R
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC304T-I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164335 - MODULE SKT FOR 10X10 PM3 44TQFPDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC33FJ16MC304T-I/MLTR

3.5
The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
ALU is 16 bits wide and is capable of addition, subtraction,
bit shifts and logic operations. Unless otherwise
mentioned, arithmetic operations are 2’s complement in
nature. Depending on the operation, the ALU can affect
the values of the Carry (C), Zero (Z), Negative (N),
Overflow (OV) and Digit Carry (DC) Status bits in the SR
register. The C and DC Status bits operate as Borrow and
Digit Borrow bits, respectively, for subtraction operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
Refer to the “16-bit MCU and DSC Programmer’s Ref-
erence Manual” (DS70157) for information on the SR
bits affected by each instruction.
The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
CPU
multiplication and division. This includes a dedicated
hardware
16-bit-divisor division.
3.5.1
Using the high-speed 17-bit x 17-bit multiplier of the
DSP engine, the ALU supports unsigned, signed or
mixed-sign operation in several MCU multiplication
modes:
• 16-bit x 16-bit signed
• 16-bit x 16-bit unsigned
• 16-bit signed x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit unsigned
• 16-bit unsigned x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit signed
• 8-bit unsigned x 8-bit unsigned
3.5.2
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
1.
2.
3.
4.
The quotient for all divide instructions ends up in W0
and the remainder in W1. 16-bit signed and unsigned
DIV instructions can specify any W register for both the
16-bit divisor (Wn) and any W register (aligned) pair
(W(m + 1):Wm) for the 32-bit dividend. The divide
algorithm takes one cycle per bit of divisor, so both
32-bit/16-bit and 16-bit/16-bit instructions take the
same number of cycles to execute.
© 2011 Microchip Technology Inc.
32-bit signed/16-bit signed divide
32-bit unsigned/16-bit unsigned divide
16-bit signed/16-bit signed divide
16-bit unsigned/16-bit unsigned divide
incorporates
Arithmetic Logic Unit (ALU)
MULTIPLIER
DIVIDER
multiplier
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
hardware
and
support
support
hardware
for
both
for
3.6
The DSP engine consists of a high-speed 17-bit x
17-bit multiplier, a barrel shifter and a 40-bit
adder/subtracter (with two target accumulators, round
and saturation logic).
The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
is a single-cycle instruction flow architecture; therefore,
concurrent operation of the DSP engine with MCU
instruction flow is not possible. However, some MCU ALU
and DSP engine resources can be used concurrently by
the same instruction (e.g., ED, EDAC).
The DSP engine can also perform inherent accumula-
tor-to-accumulator operations that require no additional
data. These instructions are ADD, SUB and NEG.
The DSP engine has options selected through bits in
the CPU Core Control register (CORCON), as listed
below:
• Fractional or integer DSP multiply (IF)
• Signed or unsigned DSP multiply (US)
• Conventional or convergent rounding (RND)
• Automatic saturation on/off for ACCA (SATA)
• Automatic saturation on/off for ACCB (SATB)
• Automatic saturation on/off for writes to data
• Accumulator Saturation mode selection (ACCSAT)
A block diagram of the DSP engine is shown in
Figure
TABLE 3-1:
CLR
ED
EDAC
MAC
MAC
MOVSAC
MPY
MPY
MPY.N
MSC
memory (SATDW)
Instruction
3-3.
DSP Engine
DSP INSTRUCTIONS
SUMMARY
No change in A
A = A + (x – y)
A = A + (x * y)
A = A – x • y
Operation
Algebraic
A = (x - y)
A = A + x
A = – x • y
A = x • y
A = x
A = 0
2
2
2
2
DS70283H-page 25
ACC Write
Back
Yes
Yes
Yes
Yes
No
No
No
No
No
No