EVAL-AD1937AZ Analog Devices Inc, EVAL-AD1937AZ Datasheet - Page 12

• Manufacturer Part Number: EVAL-AD1937AZ
• Description: EB Single Chip Codec 4 ADCs W/Diff Outp
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD1937AZ

• Main Purpose: Audio, CODEC
• Utilized Ic / Part: AD1937
• Primary Attributes: 24-Bit, 192 kHz, 4 ADCs: 107dB Dynamic Range, 8 DACs: 112dB Dynamic Range
• Secondary Attributes: Time Division Multiplexed (TDM), I2C, and SPI Interface, Popguard® Technology
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Embedded: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD1937
Pin No.
23
24
25
26
27
28
29
30
31
34
35
36
37
38
39
40
41
42
43
47
49, 50, 63, 64
52
53
54
55
56
57
58
59
60
61
1
I = input, O = output.
Type
I
I
O
I/O
O
I/O
I/O
I
I/O
I
I
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
O
1
VSUPPLY
VSENSE
Mnemonic
VDRIVE
ASDATA2
ASDATA1
ABCLK
ALRCLK
ADDR0
SDA
SCL
ADDR1
DAC1LP
DAC1LN
DAC1RP
DAC1RN
DAC2LP
DAC2LN
DAC2RP
DAC2RN
FILTR
NC
CM
ADC1LP
ADC1LN
ADC1RP
ADC1RN
ADC2LP
ADC2LN
ADC2RP
ADC2RN
LF
Description
5 V Input to Regulator, Emitter of Pass Transistor.
Connect 3.3 V Regulator Output, Collector of Pass Transistor, to This Pin.
Drive for Base of Pass Transistor.
ADC Serial Data Output 2. Data Output from ADC2/TDM ADC data in/AUX DAC1 data out (to
external DAC1).
ADC Serial Data Output 1. Data Output from ADC1/TDM ADC data out/TDM data out.
Bit Clock for ADCs. Can be programmed as input or output in all modes.
Frame Clock for ADCs. Can be programmed as input or output in all modes.
I
Control Data Port (I
Control Clock Port (I
I
DAC1 Left Positive Output.
DAC1 Left Negative Output.
DAC1 Right Positive Output.
DAC1 Right Negative Output.
DAC2 Left Positive Output.
DAC2 Left Negative Output.
DAC2 Right Positive Output.
DAC2 Right Negative Output.
Analog Voltage Reference Filter Capacitor Connection. Bypass with 10 μF||100 nF to AGND.
No Connect.
Common-Mode Reference Filter Capacitor Connection. Bypass with 47 μF||100 nF to AGND.
ADC1 Left Positive Input.
ADC1 Left Negative Input.
ADC1 Right Positive Input.
ADC1 Right Negative Input.
ADC2 Left Positive Input.
ADC2 Left Negative Input.
ADC2 Right Positive Input.
ADC2 Right Negative Input.
PLL Loop Filter, Return to AVDD.
2
2
C Address Assignment.
C Address Assignment.
Rev. B | Page 12 of 36
2
C).
2
C).