EVAL-AD1937AZ Analog Devices Inc, EVAL-AD1937AZ Datasheet - Page 26

• Manufacturer Part Number: EVAL-AD1937AZ
• Description: EB Single Chip Codec 4 ADCs W/Diff Outp
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD1937AZ

• Main Purpose: Audio, CODEC
• Utilized Ic / Part: AD1937
• Primary Attributes: 24-Bit, 192 kHz, 4 ADCs: 107dB Dynamic Range, 8 DACs: 112dB Dynamic Range
• Secondary Attributes: Time Division Multiplexed (TDM), I2C, and SPI Interface, Popguard® Technology
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Embedded: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD1937
ADDITIONAL MODES
The AD1937 offers several additional modes for board level
design enhancements. To reduce the EMI in board level design,
serial data can be transmitted without an explicit BCLK. See
Figure 28 and Figure 29 for an example of a DAC TDM data
transmission mode that does not require high speed DBCLK.
This configuration is applicable when the AD1937 master
clock is generated by the PLL with the DLRCLK as the PLL
reference frequency.
T
DM DSDATAn
DSDATAn
DLRC
INTERNAL
DBCL
DLRCLK
DBCLK
LK
INTERNAL
K
DSDATAx
DLRCLK
DBCLK
Figure 29. Serial DAC Data Transmission in TDM Format Without DBCLK; 128 to 512 BCLKs per Frame TDM Mode
Figure 28. Serial DAC Data Transmission in TDM Format Without DBCLK; 2-Channel 64 BCLKs per Frame Mode
(Applicable Only If PLL Locks to DLRCLK; This Mode Is Also Available in the ADC Serial Data Port)
(Applicable Only If PLL Locks to DLRCLK; This Mode Is Also Available in the ADC Serial Data Port)
MSB
(Applicable in Stereo and TDM, Useful for High Frequency TDM Transmission;
Figure 30. I
32 BITS
This Mode Is Also Available in the ADC Serial Data Port)
DATA MUST BE VALID
AT THIS BCLK EDGE
2
S Pipeline Mode in DAC Serial Data Transmission
Rev. B | Page 26 of 36
To relax the requirement for the setup time of the AD1937 in
cases of high speed TDM data transmission, the AD1937 can
latch in the data using the falling edge of DBCLK. This effec-
tively dedicates the entire BCLK period to the setup time. This
mode is useful in cases where the source has a large delay time
in the serial data driver. Figure 30 shows this pipeline mode of
data transmission.
Both the BCLK-less and pipeline modes are available on the
ADC serial data port.