EVAL-AD9835EBZ Analog Devices Inc, EVAL-AD9835EBZ Datasheet
EVAL-AD9835EBZ
Specifications of EVAL-AD9835EBZ
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EVAL-AD9835EBZ Summary of contents
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FEATURES 5 V Power Supply 50 MHz Speed On-Chip COS Look-Up Table On-Chip 10-Bit DAC Serial Loading Power-Down Option 200 mW Power Consumption 16-Lead TSSOP APPLICATIONS DDS Tuning Digital Demodulation FSELECT MCLK BIT FSELECT FREQ0 REG FREQ1 REG 16-BIT ...
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AD9835–SPECIFICATIONS Parameter SIGNAL DAC SPECIFICATIONS Resolution Update Rate (f ) MAX IOUT Full Scale Output Compliance DC Accuracy Integral Nonlinearity Differential Nonlinearity 2 DDS SPECIFICATIONS Dynamic Specifications Signal-to-Noise Ratio Total Harmonic Distortion Spurious Free Dynamic Range (SFDR) Narrow Band ( ...
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TIMING CHARACTERISTICS Limit MIN MAX Parameter (B Version SCLK – ...
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AD9835 ABSOLUTE MAXIMUM RATINGS +25 C unless otherwise noted) A AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . –0 ...
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Pin # Mnemonic Function ANALOG SIGNAL AND REFERENCE 1 FS ADJUST Full-Scale Adjust Control. A resistor (R the magnitude of the full-scale DAC current. The relationship between R as follows: 2 REFIN Voltage Reference Input. The AD9835 can be used ...
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AD9835 Table I. Control Registers Register Size Description FREQ0 REG 32 Bits Frequency Register 0. This de- fines the output frequency, when FSELECT = fraction of the MCLK frequency. FREQ1 REG 32 Bits Frequency Register 1. This ...
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AD9835 –20 AVDD = DVDD = +5V –30 –40 50MHz –50 30MHz –60 –70 10MHz –80 0.044 0.084 0.124 0.164 0.204 0.244 f /f OUT MCLK Figure 9. Wide Band SFDR vs OUT Frequencies 56 f OUT 55 ...
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START RBW 1kHz VBW 3kHz Figure 15 MHz 9.1 MHz. Frequency MCLK OUT Word = 2E978D50 0Hz START RBW 1kHz VBW 3kHz Figure 16 MHz 11.1 MHz. Frequency MCLK ...
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AD9835 CIRCUIT DESCRIPTION The AD9835 provides an exciting new level of integration for the RF/Communications system designer. The AD9835 com- bines the Numerical Controlled Oscillator (NCO), COS Look-Up Table, Frequency and Phase Modulators, and a Digital-to- Analog Converter on a ...
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FSYNC should be taken high again. The SCLK can be con- tinuous or, alternatively, the SCLK can idle high or low be- tween write operations. When writing to a frequency/phase register, the first four bits identify whether a frequency or ...
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AD9835 PHASEREG <3:0> = DELTA PHASE< 3> WAIT 6 MCLK CYCLES (8 MCLK CYCLES IF SYNC = *6.25*R OUT REFIN CHANGE FSELECT Figure 20. Flowchart for AD9835 Initialization and Operation INITIALIZATION* CONTROL REGISTER WRITE ...
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APPLICATIONS The AD9835 contains functions that make it suitable for modulation applications. The part can be used to perform simple modulation such as FSK. More complex modulation schemes such as GMSK and QPSK can also be implemented using the AD9835. ...
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... FSYNC Prototyping Area SDATA An area is available on the evaluation board where the user can SCLK add additional circuits to the evaluation test set. Users may want to build custom analog filters for the output or add buffers and operational amplifiers to be used in the final application. ...
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... FSYNC AD9835 11 PSEL1 LK1 12 PSEL0 LK2 10 FSELECT LK3 6 MCLK DGND AGND 5 DVDD U3 OUT XTAL1 DGND Figure 29. Evaluation Board Layout Links LK1–LK3 LK4 Switch SW Sockets MCLK, PSEL0, PSEL1, FSELECT, IOUT, REFIN Connectors J1 J2, J3 –15– AD9835 AVDD C2 AVDD 0 10nF 16 COMP REFIN ...
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AD9835 16-Lead Thin Shrink Small Outline Package (TSSOP) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). (RU-16) 0.201 (5.10) 0.193 (4.90 PIN 1 0.006 (0.15) 0.0433 0.002 (0.05) (1.10) MAX 8° 0.0256 0.0118 (0.30) 0° SEATING ...