EVAL-ADF7021-VDB2Z Analog Devices Inc, EVAL-ADF7021-VDB2Z Datasheet - Page 22

• Manufacturer Part Number: EVAL-ADF7021-VDB2Z
• Description: 868 - 870MHz - EVALUATION BOARD
• Manufacturer: Analog Devices Inc
• Type: Transceiverr

Specifications of EVAL-ADF7021-VDB2Z

• Frequency: 868MHz ~ 870MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADF7021
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADF7021-V
The free design tool ADIsimSRD™ Design Studio can also be
used to design loop filters for the ADF7021-V. See the ADIsimSRD
Design Studio website (www.analog.com/adisimsrd) for details).
N Counter
The feedback divider in the ADF7021-V PLL consists of an
8-bit integer counter (set using Register 0, Bits[DB26:DB19])
and a 15-bit, Σ-Δ fractional-N divider (set using Register 0,
Bits[DB18:DB4]). The integer counter is the standard pulse-
swallow type that is common in PLLs. It sets the minimum
integer divide value to 23. The fractional divide value provides
very fine resolution at the output, where the output frequency
of the PLL is calculated as
When RF_DIVIDE_BY_2 is enabled (see the Voltage
Controlled Oscillator (VCO) section), this formula becomes
The combination of INTEGER_N (maximum = 255) and
FRACTIONAL_N (maximum = 32,768/32,768) gives a
maximum N divider of 255 + 1. Therefore, the minimum
usable PFD is
For example, when operating in the European 868 MHz to
870 MHz band, PFD
Voltage Regulators
The ADF7021-V contains four regulators to supply stable
voltages to the part. The nominal regulator voltage is 2.3 V.
Regulator 1 requires a 3.9 Ω resistor and a 100 nF capacitor in
series between CREG1 and ground, whereas the other regula-
tors require a 100 nF capacitor connected between CREGx and
ground. When CE is high, the regulators and other associated
circuitry are powered on, drawing a total supply current of
2 mA. Bringing the CE pin low disables the regulators, reduces
the supply current to less than 1 μA, and erases all values held
in the registers.
PFD
f
f
REFERENCE IN
OUT
OUT
MIN
÷R
=
=
XTAL
XTAL
(Hz)
R
R
CHARGE
FRACTIONAL_N
PUMP
PFD/
=
×
×
MIN
Figure 35. Fractional-N PLL
Maximum
0.5
⎛
⎜ ⎜
⎝
INTEGER
= 3.4 MHz.
×
⎛
⎜
⎝
INTEGER_N
Σ-Δ MODULATOR
THIRD-ORDER
Required
_
N
(
255
+
FRACTIONAL
+
+
Output
INTEGER_N
1
FRACTIONAL
)
VCO
÷N
2
15
Frequency
2
15
_
N
_
⎞
⎟ ⎟
⎠
Rev. 0 | Page 22 of 60
N
⎞
⎟
⎠
The serial interface operates from a regulator supply. Therefore,
to write to the part, CE must be high and the regulator voltage
must be stabilized. Regulator status (CREG4) can be monitored
using the REGULATOR_READY signal from the MUXOUT pin.
MUXOUT
The MUXOUT pin allows access to various digital points in the
ADF7021-V. The state of MUXOUT is controlled in Register 0,
Bits[DB31:DB29].
REGULATOR_READY
REGULATOR_READY is the default setting on MUXOUT after
the transceiver is powered up. The power-up time of the regulator
is typically 50 μs. Because the serial interface is powered from
the regulator, the regulator must be at its nominal voltage before
the ADF7021-V can be programmed. The regulator status can
be monitored at MUXOUT. When the regulator ready signal on
MUXOUT is high, programming of the ADF7021-V can begin.
FILTER_CAL_COMPLETE
MUXOUT can be set to FILTER_CAL_COMPLETE. This signal
goes low for the duration of both a coarse IF filter calibration
and a fine IF filter calibration. It can be used as an interrupt to
a microcontroller to signal the end of the IF filter calibration.
DIGITAL_LOCK_DETECT
DIGITAL_LOCK_DETECT indicates when the PLL has locked.
The lock detect circuit is located at the PFD. When the phase
error on five consecutive cycles is less than 15 ns, lock detect is
set high. Lock detect remains high until a 25 ns phase error is
detected at the PFD.
RSSI_READY
MUXOUT can be set to RSSI_READY. This indicates that the
internal analog RSSI has settled and that a digital RSSI readback
can be performed.
Tx_Rx
Tx_Rx signifies whether the ADF7021-V is in transmit or
receive mode. When in transmit mode, this signal is low.
When in receive mode, this signal is high. It can be used to
control an external Tx/Rx switch.
REGULATOR_READY (DEFAULT)
FILTER_CAL_COMPLETE
DIGITAL_LOCK_DETECT
LOGIC_ZERO
RSSI_READY
LOGIC_ONE
TRISTATE
Tx_Rx
Figure 36. MUXOUT Circuit
MUX
CONTROL
GND
V
DD
MUXOUT