EVAL-ADF7021-VDB2Z Analog Devices Inc, EVAL-ADF7021-VDB2Z Datasheet - Page 31

• Manufacturer Part Number: EVAL-ADF7021-VDB2Z
• Description: 868 - 870MHz - EVALUATION BOARD
• Manufacturer: Analog Devices Inc
• Type: Transceiverr

Specifications of EVAL-ADF7021-VDB2Z

• Frequency: 868MHz ~ 870MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADF7021
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2FSK Bit Slicer/Threshold Detection
2FSK demodulation can be implemented using the correlator
FSK demodulator or the linear FSK demodulator. In both cases,
threshold detection is used for data recovery at the output of the
postdemodulator filter.
The output signal levels of the correlator demodulator are always
centered about 0. Therefore, the slicer threshold level can be
fixed at 0, and the demodulator performance is independent of
the run-length constraints of the transmit data bit stream. This
results in robust data recovery that does not suffer from the
classic baseline wander problems that exist in more traditional
FSK demodulators.
When the linear demodulator is used for 2FSK demodulation,
the output of the envelope detector is used as the slicer threshold,
and this output tracks frequency errors that are within the IF
filter bandwidth.
3FSK and 4FSK Threshold Detection
4FSK demodulation is implemented using the correlator
demodulator followed by the postdemodulator filter and
threshold detection. The output of the postdemodulator filter
is a four-level signal that represents the transmitted symbols
(−3, −1, +1, +3). Threshold detection of 4FSK requires three
threshold settings: one that is always fixed at 0 and two that are
programmable and are symmetrically placed above and below 0
using the 3FSK/4FSK_SLICER_THRESHOLD bits (Register 13,
Bits[DB10:DB4]).
3FSK demodulation is implemented using the correlator demod-
ulator, followed by a postdemodulator filter. The output of the
postdemodulator filter is a three-level signal that represents the
transmitted symbols (−1, 0, +1). Data recovery of 3FSK can be
implemented using threshold detection or Viterbi detection.
Threshold detection is implemented using two thresholds that
are programmable and are symmetrically placed above and
below 0 using the 3FSK/4FSK_SLICER_THRESHOLD bits
(Register 13, Bits[DB10:DB4]).
3FSK Viterbi Detection
Viterbi detection of 3FSK operates on a four-state trellis and is
implemented using two interleaved Viterbi detectors operating
at half the symbol rate. The Viterbi detector is enabled by
Register 13, Bit DB11.
To facilitate different run-length constraints in the transmitted
bit stream, the Viterbi path memory length is programmable in
steps of 4 bits, 6 bits, 8 bits, or 32 bits by setting the VITERBI_
PATH_MEMORY bits (Register 13, Bits[DB14:DB13]). This
value should be set equal to or greater than the maximum
number of consecutive 0s in the interleaved transmit bit stream.
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When used with Viterbi detection, the receiver sensitivity
for 3FSK is typically 3 dB greater than that obtained using
threshold detection. When the Viterbi detector is enabled,
however, the receiver bit latency is increased by twice the
Viterbi path memory length.
Clock and Data Recovery (CDR)
An oversampled digital clock and data recovery (CDR) PLL is
used to resynchronize the received bit stream to a local clock in
all modulation modes. The oversampled clock rate of the PLL
(CDR CLK) must be set at 32 times the symbol rate (see the
Register 3—Transmit/Receive Clock Register section). The maxi-
mum data/symbol rate tolerance of the CDR PLL is determined
by the number of zero-crossing symbol transitions in the trans-
mitted packet. For example, if using 2FSK with a 101010 preamble,
a maximum tolerance of ±3.0% of the data rate is achieved.
However, this tolerance is reduced during recovery of the
remainder of the packet, where symbol transitions may not be
guaranteed to occur at regular intervals. To maximize the data
rate tolerance of the CDR, some form of encoding and/or data
scrambling is recommended that guarantees a number of
transitions at regular intervals.
For example, using 2FSK with Manchester-encoded data
achieves a data rate tolerance of ±2.0%.
The CDR PLL is designed for fast acquisition of the recovered
symbols during preamble and typically achieves bit synchro-
nization within five-symbol transitions of preamble.
In 4FSK modulation, the tolerance using the +3, −3, +3, −3
preamble is ±3% of the symbol rate (or ±1.5% of the data rate).
However, this tolerance is reduced during recovery of the
remainder of the packet, where symbol transitions may not
be guaranteed to occur at regular intervals. To maximize the
symbol/data rate tolerance of the CDR, the remainder of the
4FSK packet should be constructed so that the transmitted
symbols retain close to dc-free properties by using data scram-
bling and/or by inserting specific dc-balancing symbols into the
transmitted bit stream at regular intervals, such as after every
8 or 16 symbols.
In 3FSK modulation, the linear convolutional encoder scheme
guarantees that the transmitted symbol sequence is dc-free,
facilitating symbol detection. However, Tx data scrambling is
recommended to limit the run length of 0 symbols in the
transmit bit stream. Using 3FSK, the CDR data rate tolerance is
typically ±0.5%.
ADF7021-V