EVAL-ADV7179EBZ Analog Devices Inc, EVAL-ADV7179EBZ Datasheet - Page 26

• Manufacturer Part Number: EVAL-ADV7179EBZ
• Description: EVALUATION BOARD
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADV7179EBZ

• Main Purpose: Video, Video Processing
• Embedded: No
• Utilized Ic / Part: ADV7179
• Primary Attributes: NTSC/PAL Digital Video Encoder
• Secondary Attributes: I²C Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV7174/ADV7179
Frequency Registers 1, 2, and 3. The subcarrier frequency
registers should not be accessed independently.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCLOCK high period,
the user should issue only one start condition, one stop condition,
or a single stop condition followed by a single start condition. If
an invalid subaddress is issued by the user, the ADV7174/
ADV7179 cannot issue an acknowledge and returns to the idle
condition. If in auto-increment mode the user exceeds the
highest subaddress, the following action is taken:
1.
2.
In read mode, the highest subaddress register contents
continues to be output until the master device issues a no-
acknowledge. This indicates the end of a read. A no-
acknowledge condition is when the SDATA line is not
pulled low on the ninth pulse.
In write mode, the data for the invalid byte is not loaded
into any subaddress register, a no-acknowledge is issued by
the ADV7174/ADV7179, and the part returns to the idle
condition.
SEQUENCE
SEQUENCE
WRITE
READ
S SLAVE ADDR A(S)
S SLAVE ADDR A(S)
S = START BIT
P = STOP BIT
LSB = 0
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
SUB ADDR
SUB ADDR
Figure 36. Write and Read Sequences
A(S)
A(S) S SLAVE ADDR
Rev. B | Page 26 of 52
DATA
LSB = 1
A(S)
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
Figure 35 illustrates an example of data transfer for a read
sequence and the start and stop conditions.
Figure 36 shows bus write and read sequences.
SCLOCK
REGISTER ACCESSES
The MPU can write to or read from all of the ADV7174/
ADV7179 registers except the subaddress register, which is a
write-only register. The subaddress register determines which
register the next read or write operation accesses. All commu-
nications with the part through the bus start with an access to
the subaddress register. A read/write operation is performed
from to the target address, which then increments to the next
address until a stop command on the bus is performed.
A(S)
SDATA
START ADDR R/W ACK SUBADDRESS ACK
DATA
S
1–7
DATA
A(M)
8
Figure 35. Bus Data Transfer
9
A(S)
1 –7
P
DATA
8
9
A(M)
1–7
DATA
P
8
ACK
9
STOP
P