FM18W08-SGTR Ramtron, FM18W08-SGTR Datasheet - Page 2

• Manufacturer Part Number: FM18W08-SGTR
• Description: SOIC28 T&R
• Manufacturer: Ramtron

Pin Description
Functional Truth Table
Note: The /OE pin controls only the DQ output buffers.
Rev. 2.1
Jan. 2012
Pin Name
A(14:0)
DQ(7:0)
/CE
/OE
/WE
VDD
VSS
/CE
H

L
L
WE
CE
OE
A(14:0)
Supply
Supply
/WE
Type
Input
Input
Input
Input
I/O
X
X
H

Decoder
Address
Latch &
Control
Logic
Description
Address: The 15 address lines select one of 32,768 bytes in the F-RAM array. The
address value is latched on the falling edge of /CE.
Data: 8-bit bi-directional data bus for accessing the F-RAM array.
Chip Enable: /CE selects the device when low. Asserting /CE low causes the
address to be latched internally. Address changes that occur after /CE goes low
will be ignored until the next falling edge occurs.
Output Enable: Asserting /OE low causes the FM18W08 to drive the data bus
when valid data is available. Deasserting /OE high causes the DQ pins to be tri-
stated.
Write Enable: Asserting /WE low causes the FM18W08 to write the contents of
the data bus to the address location latched by the falling edge of /CE.
Supply Voltage
Ground
Function
Standby/Precharge
Latch Address (and Begin Write if /WE=low)
Read
Write
Figure 1. Block Diagram
A(14:0)
32,768 x 8 FRAM Array
Bus Driver
I/O Latch
DQ(7:0)
FM18W08
Page 2 of 11