KSZ8041FTLI Micrel Inc, KSZ8041FTLI Datasheet - Page 18

• Manufacturer Part Number: KSZ8041FTLI
• Description: Physical Layer Transceiver 10/100BASE-FX ( )
• Manufacturer: Micrel Inc
• Type: Transceiverr

Specifications of KSZ8041FTLI

• Number Of Drivers/receivers: 1/1
• Protocol: SMII
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-3294 - BOARD EVALUATION KSZ8041FTL
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-3347

Micrel, Inc.
Pin Description– KSZ8041MLL
December 2009
Pin Number
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
2
3
4
5
6
7
8
9
VDDIO_3.3
VDDIO_3.3
VDDA_1.8
VDDA_1.8
V1.8_OUT
VDDA_3.3
VDDA_3.3
Pin Name
PHYAD0
PHYAD1
PHYAD2
DUPLEX
RXD3 /
RXD2 /
RXD1 /
RXD0 /
REXT
MDIO
GND
GND
GND
GND
GND
MDC
GND
RX+
TX+
RX-
TX-
XO
XI
Type
Ipu/O
Ipd/O
Ipd/O
Ipu/O
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
I/O
I/O
I/O
I/O
I/O
I/O
O
P
P
P
P
P
P
P
I
I
(1)
Pin Function
Ground
Ground
Ground
1.8V analog V
1.8V analog V
1.8V output voltage from chip
3.3V analog V
3.3V analog V
Physical receive or transmit signal (- differential)
Physical receive or transmit signal (+ differential)
Physical transmit or receive signal (- differential)
Physical transmit or receive signal (+ differential)
Ground
Crystal feedback
This pin is used only when a 25 MHz crystal is used.
This pin is a no connect if oscillator or external clock source is used.
Crystal / Oscillator / External Clock Input
25MHz +/-50ppm
Set physical transmit output current
Connect a 6.49KŸ resistor in parallel with a 100pF capacitor to ground on this
pin. See KSZ8041MLL reference schematic.
Ground
Management Interface (MII) Data I/O
This pin requires an external 4.7KŸpull-up resistor.
Management Interface (MII) Clock Input
This pin is synchronous to the MDIO data interface.
MII Mode:
Config. Mode:
MII Mode:
Config. Mode:
MII Mode:
Config. Mode:
MII Mode:
Config Mode:
Ground
3.3V digital V
3.3V digital V
DD
DD
DD
DD
DD
DD
Receive Data Output[3]
The pull-up/pull-down value is latched as PHYADDR[0] during
power-up / reset. See “Strapping Options” section for details.
Receive Data Output[2]
The pull-up/pull-down value is latched as PHYADDR[1] during
power-up / reset. See “Strapping Options” section for details.
Receive Data Output[1]
The pull-up/pull-down value is latched as PHYADDR[2] during
power-up / reset. See “Strapping Options” section for details.
Receive Data Output[0]
reset. See “Strapping Options” section for details.
Latched as DUPLEX (register 0h, bit 8) during power-up /
18
(2)
(2)
(2)
(2)
/
/
/
/
KSZ8041TL/FTL/MLL
M9999-120909-1.2