AD9860BST Analog Devices Inc, AD9860BST Datasheet
AD9860BST
Specifications of AD9860BST
Available stocks
Related parts for AD9860BST
AD9860BST Summary of contents
Page 1
FEATURES Mixed-Signal Front-End Processor with Dual Converter Receive and Dual Converter Transmit Signal Paths Receive Signal Path Includes: Two 10-/12-Bit, 64 MSPS Sampling A/D Converters with Internal or External Independent References, Input Buffers, Programmable Gain Amplifiers, Low-Pass Decimation Filters, ...
Page 2
AD9860/AD9862–SPECIFICATIONS Tx PARAMETERS 12-/14-BIT DAC CHARACTERISTICS Resolution Maximum Update Rate Full-Scale Output Current Gain Error (Using Internal Reference) Offset Error Reference Voltage (REFIO Level) Negative Differential Nonlinearity (–DNL) Positive Differential Nonlinearity (+DNL) Integral Nonlinearity (INL) Output Capacitance Phase Noise @ ...
Page 3
Rx PARAMETERS (continued) DC ACCURACY Differential Nonlinearity Integral Nonlinearity Offset Error Gain Error Aperture Delay Aperture Uncertainty (Jitter) Input Referred Noise Reference Voltage Error REFT-REFB Error (1 V) AD9860 DYNAMIC PERFORMANCE (A IN Signal-to-Noise Ratio Signal-to-Noise and Distortion Ratio Total ...
Page 4
AD9860/AD9862 PARAMETERS (continued) POWER SUPPLY (continued) Rx Path ( MSPS) ADC Processing Blocks Disabled Decimation Filter Enabled Hilbert Filter Enabled Hilbert and Decimation Filter Enabled NOTES refers to the input data rate of the digital ...
Page 5
... The AD9860/AD9862 have been characterized to operate over the industrial temperature range (– +85 C) when operated in Half Duplex Mode. Model Temperature Range AD9860BST –40∞C to +70∞C* AD9862BST –40∞C to +70∞C* AD9860PCB AD9862PCB *The AD9860/AD9862 have been characterized to operate over the industrial temperature range (– +85 C) when operated in Half Duplex Mode. ...
Page 6
AD9860/AD9862 AUX_ADC_A1 1 PIN 1 2 AGND IDENTIFIER 3 AVDD AVDD 4 5 SIGDELT AUX_DAC_A 6 AUX_DAC_B 7 8 AUX_DAC_C 9 AGND DLL_Lock 10 AGND AVDD OSC1 14 15 OSC2 AGND 16 17 CLKSEL 18 AVDD ...
Page 7
Pin No. Mnemonic Function Receive Pins 68/70–79 D0A to 10-/12-Bit ADC Output of D9A/D11A Receive Channel A 80/82–91 D0B to 10-/12-Bit ADC Output of D9B/D11B Receive Channel B 92 RxSYNC Synchronization Clock for Channel A and Channel B Rx Paths ...
Page 8
AD9860/AD9862 DEFINITIONS OF SPECIFICATIONS Differential Nonlinearity Error (DNL, No Missing Codes) An ideal converter exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 10-bit resolution indicate that ...
Page 9
DATA –10 4 INTERPOLATION –20 –30 –40 –50 –60 –70 –80 –90 –100 100 110 120 140 FREQUENCY – MHz TPC 1. AD9862 Tx Output 6 MHz Single Tone; CLKIN = ...
Page 10
AD9860/AD9862 0 –20 –40 –60 –80 –100 –120 FFT OUTPUT – MHz TPC 10. ADC Dual Tone FFT with Buffer Tones at 4.5 MHz and 5.5 MHz 68 11.0 66 BUFFERED BYPASS 10.5 ...
Page 11
BUFFERED BYPASS –55 2V INPUT, 1 GAIN –60 BUFFERED 2V INPUT, 1 GAIN –65 –70 –75 –80 BUFFERED 1V INPUT, 2 GAIN –85 BUFFERED BYPASS –90 1V INPUT, 2 GAIN –95 –100 0 10 100 1000 INPUT FREQUENCY – ...
Page 12
AD9860/AD9862 2 Register Name Address Bit 7 General 0 SDIO BiDir Rx Power Down 1 V (diff) REF Byp Buffer Byp Buffer B Rx Misc Digital 6 RSV ...
Page 13
REGISTER BIT DEFINITIONS REGISTER 0: GENERAL BIT 7: SDIO BiDir (Bidirectional) Default setting is low, which indicates SPI serial port uses dedi- cated input and output lines (i.e., 4-wire interface), SDIO and SDO Pins, respectively. Setting this bit high configures ...
Page 14
AD9860/AD9862 Setting this bit high enables the decimation filters and decimates the receive data by two. REGISTER 8: Tx PWRDWN BIT 5: Alt Timing Mode The timing section in the data sheet describes two timing modes, the “Normal Operation” and ...
Page 15
BIT 5: Q/I Order This register indicates the order of received complex transmit data. By default this bit is low, representing I data preceding Q data. Alternatively, if this bit is set high, the data format is defined as Q ...
Page 16
AD9860/AD9862 default, this bit is low, setting up the DLL in “slow” mode. This bit must be set high for DLL output frequencies over 64 MHz. REGISTER 25: CLKOUT BIT 7, 6: CLKOUT2 Divide Factor These bits control what rate ...
Page 17
Blank Registers Blank registers, i.e., the registers with 0 settings and no indicated function, are placeholders used throughout the register map for spacing the AD9860/AD9862 control bits in a logic fashion and, potentially can be used for future development. A ...
Page 18
AD9860/AD9862 SEN SCLK DON’T CARE R/nW 2/n1 SDIO DON’T CARE INSTRUCTION HEADER (REGISTER N) SDO DON’T CARE SEN DON’T CARE SCLK 2/n1 DON’T CARE R/nW SDIO SEN SCLK ...
Page 19
BLOCK A DAC IOUT+A PGA TxDAC IOUT–A IOUT+B PGA TxDAC IOUT–B Interpolation Stage (Block C), Fine Modulation Stage (Block D), Hilbert filter (Block E), and the Latch/Demultiplexing circuitry. DAC The DAC stage of the AD9860/AD9862 integrates a high perfor- mance ...
Page 20
AD9860/AD9862 The second interpolation filter will provide an additional 2 inter- polation for an overall 4 interpolation. The second filter tap filter. It suppresses out-of-band signals more. The flat passband response (less than ...
Page 21
In most systems, the DAC (and each up-converter stage) requires analog filtering to meet spectral mask and out-of-band spurious emissions requirements. Digital interpolation (Block C) and Hilbert filtering (Block E) can be used to relax some of the system analog ...
Page 22
AD9860/AD9862 BLOCK A BLOCK B VIN+A 1 PGA VIN–A VIN+B 1 PGA VIN–B RECEIVE SECTION COMPONENTS The receive block is configurable to process input signals of dif- ferent formats and has special features such as an input buffer, gain stage, ...
Page 23
The internal references can also be disabled (powered down) and driven externally to provide a different input voltage range or low drift reference external V is used, it should not exceed 1 ...
Page 24
AD9860/AD9862 The output will be latched using some configuration of CLKOUT1 or CLKOUT2 edges as defined in the Clock Overview section of the data sheet. The Rx path available options include bypassing the input buffer, RxPGA control and using the ...
Page 25
Table Ia. CLKSEL Set Logic Low ADC CLKSEL Div 2 Decimate Multiplex No Mux No Decimation Mux No Div No Mux Decimation Mux Rx Data(MUXED Low No Mux No Decimation Mux Rx Data(MUXED Div No Mux ...
Page 26
AD9860/AD9862 For the Normal Operation mode, the Tx timing is based on a clock derived from the DLL output, while the Rx clock is unaffected by the DLL setting. The Alternative Operation mode, timing utilizes the output of the DLL ...
Page 27
Tx Path (Normal Operation) The DAC update rate, the Tx input data rate, and the rate of CLKOUT2 (clock used to latch Tx input data) are the parameters of interest for the transmit path data. These parameters, in addition to ...
Page 28
AD9860/AD9862 The timing block diagrams in Figures 10 and 11 show how the various clocks of the single and dual Tx path are affected by the various register settings. For dual Tx data, an option to redirect demultiplexed data to ...
Page 29
Table IV. Normal Operation Mode Master Timing Guide ...
Page 30
AD9860/AD9862 The timing block diagrams in Figures 14 and 15 show how the various clocks of the single and dual Tx path are affected by the various register settings. For dual Tx data, an option to redirect demultiplexed data to ...
Page 31
Conversion is initiated by writing a logic high to one or both of the Start register bits, Register D34 B0 (StartA) and D34 B3 (StartB). When the conversion is complete, the straight binary, 10-bit output data of the AUX ADC ...
Page 32
AD9860/AD9862 10 6 1.45 2 1.40 1.35 SEATING PLANE VIEW A ROTATED 90 CCW OUTLINE DIMENSIONS 128-Lead Plastic Quad Flatpack [LQFP] (ST-128B) Dimensions shown in millimeters 1.60 0.75 MAX 0.60 0.45 128 1 SEATING PLANE 0.20 0.09 VIEW A 7 ...