AD9861BCP-80 Analog Devices Inc, AD9861BCP-80 Datasheet - Page 48

• Manufacturer Part Number: AD9861BCP-80
• Description: IC FRONT-END MIXED SGNL 64-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9861BCP-80

• Rohs Status: RoHS non-compliant
• Rf Type: WLL, WLAN
• Features: 10-bit ADC(s), 10-bit DAC(s)
• Package / Case: 64-VFQFN, CSP Exposed Pad

AD9861
Table 25 shows typical output delay times for the AD9861 in the various mode configurations.
Table 25. AD9861 Rx Data Latch Timing
Mode No.
1
2
4
5
7
8
10
Configuration without Serial Port Interface
(Using Mode Pins)
The AD9861 can be configured using mode pins if a serial port interface is not available. This section applies only to configuring the
AD9861 without an SPI. Refer is the Digital Block, Configuring with Mode Pins section for further information.
When using the mode pin option, the pins shown in Table 26 are used to configured the AD9861.
Table 26. Using Mode Pin (SPI Disabled) to Configure Timing (SPI_CS, Pin 64, Must Be Tied Low)
Clock Mode
Mode 1 (FD)
Mode 4 (HD20)
Mode 7 (HD10)
1
Pin 17 (IFACE2) is an output clock in FD mode.
Mode Name
FD
Optional FD
HD20
Optional HD20
HD10
Optional HD10
Clone
Interpolation
Setting
2×
4×
1×
2×
4×
2×
4×
t
+2.5 ns
+1 ns
+1 ns
+2 ns
−1.5 ns
−0.5 ns
−1.5 ns
+0.5 ns
+0 ns
+1.5 ns
OD
Data Delay [ns]
PLL Setting
2×
4×
Bypassed
2×
4×
2×
4×
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FD/ HD
Pin 3
1
0
0
Relative to:
Relative to IFACE2 rising edge
Relative to IFACE3 rising edge
Relative To IFACE3 rising edge
IFACE2 (RxSYNC) relative to LSB
Relative to IFACE3 rising edge
Relative to IFACE3 rising edge
Relative to IFACE3 rising edge
Relative to IFACE3 rising edge
U12 (RxSYNC) relative to LSB
Relative to IFACE3 rising edge
10/ 20
Pin 17
N/A
0
1
1
Interp1,Interp0
Pin 1, Pin 2
0, 1
1, 0
0, 0
0, 1
1, 0
0, 1
1, 0