LTC2242IUP-12 Linear Technology, LTC2242IUP-12 Datasheet - Page 10

• Manufacturer Part Number: LTC2242IUP-12
• Description: IC,A/D CONVERTER,SINGLE,12-BIT,CMOS,LLCC,64PIN
• Manufacturer: Linear Technology

LTC2242-12
PI FU CTIO S
(LVDS Mode)
AIN
AIN
REFHA (Pins 5, 6): ADC High Reference. Bypass to
Pins 7, 8 with 0.1µF ceramic chip capacitor, to Pins 11, 12
with a 2.2µF ceramic capacitor and to ground with 1µF
ceramic capacitor.
REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5,
6 with 0.1µF ceramic chip capacitor. Do not connect to
Pins 11, 12.
REFHB (Pins 9, 10): ADC High Reference. Bypass to
Pins 11, 12 with 0.1µF ceramic chip capacitor. Do not
connect to Pins 5, 6.
REFLA (Pins 11, 12): ADC Low Reference. Bypass to
Pins 9, 10 with 0.1µF ceramic chip capacitor, to Pins 5, 6
with a 2.2µF ceramic capacitor and to ground with 1µF
ceramic capacitor.
V
GND with 0.1µF ceramic chip capacitors.
GND (Pins 16, 61, 64): ADC Power Ground.
ENC
positive edge.
ENC
starts on the negative edge. Bypass to ground with 0.1µF
ceramic for single-ended ENCODE signal.
SHDN (Pin 19): Shutdown Mode Selection Pin. Connect-
ing SHDN to GND and OE to GND results in normal
operation with the outputs enabled. Connecting SHDN to
GND and OE to V
outputs at high impedance. Connecting SHDN to V
OE to GND results in nap mode with the outputs at high
impedance. Connecting SHDN to V
results in sleep mode with the outputs at high impedance.
OE (Pin 20): Output Enable Pin. Refer to SHDN pin
function.
D0
30, 31, 32, 37, 38, 39, 40, 43, 44, 45, 46, 47, 48, 51, 52,
53, 54): LVDS Digital Outputs. All LVDS outputs require
differential 100Ω termination resistors at the LVDS re-
ceiver. D11
10
DD
–
U
+
–
/D0
+
–
(Pins 13, 14, 15, 62, 63): 2.5V Supply. Bypass to
(Pins 1, 2): Positive Differential Analog Input.
(Pins 3, 4): Negative Differential Analog Input.
(Pin 17): Encode Input. Conversion starts on the
(Pin 18): Encode Complement Input. Conversion
+
to D11
U
–
/D11
–
/D11
+
DD
is the MSB.
U
results in normal operation with the
+
(Pins 21, 22, 23, 24, 27, 28, 29,
DD
and OE to V
DD
and
DD
OGND (Pins 25, 33, 41, 50): Output Driver Ground.
OV
Drivers. Bypass to ground with 0.1µF ceramic chip
capacitor.
CLKOUT
Output. Latch data on rising edge of CLKOUT
of CLKOUT
OF
High when an over or under flow has occurred.
LVDS (Pin 57): Output Mode Selection Pin. Connecting
LVDS to 0V selects full rate CMOS mode. Connecting
LVDS to 1/3V
neous update. Connecting LVDS to 2/3V
CMOS mode with interleaved update. Connecting LVDS to
V
MODE (Pin 58): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and turns the clock duty cycle
stabilizer off. Connecting MODE to 1/3V
binary output format and turns the clock duty cycle stabilizer
on. Connecting MODE to 2/3V
output format and turns the clock duty cycle stabilizer on.
Connecting MODE to V
format and turns the clock duty cycle stabilizer off.
SENSE (Pin 59): Reference Programming Pin. Connecting
SENSE to V
input range. Connecting SENSE to V
reference and a ±1V input range. An external reference
greater than 0.5V and less than 1V applied to SENSE
selects an input range of ±V
input range.
V
Bias. Bypass to ground with 2.2µF ceramic chip capacitor.
GND (Exposed Pad) (Pin 65): ADC Power Ground. The
exposed pad on the bottom of the package needs to be
soldered to ground.
DD
CM
–
DD
/OF
selects LVDS mode.
(Pin 60): 1.25V Output and Input Common Mode
(Pins 26, 34, 42, 49): Positive Supply for the Output
+
–
(Pins 55 to 56): LVDS Over/Under Flow Output.
/CLKOUT
+
CM
.
DD
selects the internal reference and a ±0.5V
selects demux CMOS mode with simulta-
+
(Pins 35 to 36): LVDS Data Valid
DD
selects 2’s complement output
SENSE
DD
selects 2’s complement
. ±1V is the largest valid
DD
selects the internal
DD
DD
selects demux
selects offset
–
, falling edge
224212f