LTC2242IUP-12 Linear Technology, LTC2242IUP-12 Datasheet - Page 15

• Manufacturer Part Number: LTC2242IUP-12
• Description: IC,A/D CONVERTER,SINGLE,12-BIT,CMOS,LLCC,64PIN
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When ENC is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that ENC transitions from low to high, the sampled input
is held. While ENC is high, the held input voltage is
buffered by the S/H amplifier which drives the first pipelined
ADC stage. The first stage acquires the output of the S/H
during this high phase of ENC. When ENC goes back low,
the first stage produces its residue which is acquired by
the second stage. At the same time, the input S/H goes
back to acquiring the analog input. When ENC goes back
high, the second stage produces its residue which is
acquired by the third stage. An identical process is re-
peated for the third and fourth stages, resulting in a fourth
stage residue that is sent to the fifth stage ADC for final
evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2242-12
CMOS differential sample-and-hold. The analog inputs are
connected to the sampling capacitors (C
NMOS transistors. The capacitors shown attached to each
input (C
tance associated with each input.
During the sample phase when ENC is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to, and track the differential input voltage.
PARASITIC
) are the summation of all other capaci-
U
U
W
SAMPLE
U
) through
When ENC transitions from low to high, the sampled input
voltage is held on the sampling capacitors. During the hold
phase when ENC is high, the sampling capacitors are
disconnected from the input and the held voltage is passed
to the ADC core for processing. As ENC transitions from
high to low, the inputs are reconnected to the sampling
capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportional to the change in voltage between samples will
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
Common Mode Bias
For optimal performance the analog inputs should be
driven differentially. Each input should swing ±0.5V for
the 2V range or ±0.25V for the 1V range, around a
common mode voltage of 1.25V. The V
60) may be used to provide the common mode bias level.
V
to set the DC input level or as a reference level to an op amp
CM
ENC
ENC
A
A
IN
IN
+
–
+
–
can be tied directly to the center tap of a transformer
LTC2242-12
10Ω
10Ω
1.5V
1.5V
6k
6k
V
V
Figure 2. Equivalent Input Circuit
DD
DD
V
DD
C
1.8pF
C
1.8pF
PARASITIC
PARASITIC
LTC2242-12
CM
14Ω
14Ω
R
R
output pin (Pin
ON
ON
C
C
SAMPLE
SAMPLE
2pF
2pF
15
224212 F02
224212f