LTC4259ACGW-1 Linear Technology, LTC4259ACGW-1 Datasheet
LTC4259ACGW-1
Specifications of LTC4259ACGW-1
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LTC4259ACGW-1 Summary of contents
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... ESD events. Linear Technology also provides solutions for 802.3af PD applications with the LTC4257, LTC4257-1 and LTC4267. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Hot Swap is a registered trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. ...
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... DETECT n Second Point –3.5V DETECT n Open Circuit, Measured at DETECT n Pin 0mA < I < 31mA CLASS Into Short (V = 0V) DETECT U W ORDER PART TOP VIEW 1 36 OSCIN NUMBER 2 35 AUTO 3 OUT1 34 LTC4259ACGW-1 4 GATE1 33 LTC4259AIGW SENSE1 6 31 OUT2 7 30 GATE2 8 29 SENSE2 OUT3 11 26 ...
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ELECTRICAL CHARACTERISTICS temperature range, otherwise specifications are at T (Note 6). SYMBOL PARAMETER I Classification Threshold Current TCLASS Gate Driver I GATE Pin Current GON I GATE Pin Current GOFF I GATE Pin Short-Circuit Pull-Down GPD ∆V External Gate Voltage ...
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LTC4259A-1 ELECTRICAL CHARACTERISTICS temperature range, otherwise specifications are at T (Note 6). SYMBOL PARAMETER t Maximum Current Limit Duration During START Port Start-Up t Maximum Current Limit Duration After ICUT Port Start-Up DC Maximum Current Limit Duty Cycle CLMAX t ...
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W U TYPICAL PERFOR A CE CHARACTERISTICS Power On Sequence in Auto Mode PORT 3. –48V EE GND PORT DETECTION DETECTION VOLTAGE PHASE 1 PHASE 2 10V/DIV CLASSIFICATION V EE 50ms/DIV Current Limit Foldback ...
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LTC4259A TEST PORT GATE n INT Figure 2. Detect, Class and Turn-On Timing in Auto or Semiauto Modes V SENSE n V SENSE n V MIN INT ...
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DIAGRA S SCL SDA AD3 AD2 AD1 AD0 START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE SCL SDA AD3 AD2 AD1 AD0 R/W ACK START BY ...
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LTC4259A CTIO S RESET (Pin 1): Chip Reset, Active Low. When the RESET pin is low, the LTC4259A-1 is held inactive with all ports off and all internal registers reset to their power-up states. When ...
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CTIO S AGND (Pin 21): Analog Ground. AGND should be con- nected to the return from the – 48V supply. AGND and DGND should be tied together. SENSE4 (Pin 22): Port 4 Current Sense Input. ...
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LTC4259A-1 W TABLE 1. REGISTER AP 10 4259a1fa ...
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U U REGISTER FU CTIO S Interrupt Registers Interrupt (Address 00h): Interrupt Register, Read Only. A transition to logical 1 of any bit in this register will assert the INT pin (Pin 3) if the corresponding bit in the Int ...
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LTC4259A REGISTER FU CTIO S disconnect enabled independently of the state of the Osc Fail bit. See AC Disconnect under Applications Information for more details. Bit 4 indicates that V low the V UVLO level (typically –28V). Bit ...
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U U REGISTER FU CTIO S Detect/Class Enable (Address 14h): Detection and Clas- sification Enable, Read/Write. The lower four bits of this reg- ister enable the detection circuitry at the corresponding port if that port is in Auto or Semiauto ...
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LTC4259A REGISTER FU CTIO S way, the condition causing the LTC4259A-1 to pull the INT pin down must be removed before the LTC4259A-1 will be able to pull INT down again. This can be done by reading and ...
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U U APPLICATIO S I FOR ATIO The LTC4259A-1 provides a complete solution for detec- tion and powering of PD devices in an IEEE 802.3af compliant system. The LTC4259A-1 consists of four inde- pendent ports, each with the ability to ...
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LTC4259A APPLICATIO S I FOR ATIO The LTC4259A-1 checks for the signature resistance by forcing two test currents on the port (via the DETECT n pins) in sequence and measuring the resulting voltages. It then subtracts the two ...
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U U APPLICATIO S I FOR ATIO listed in Table 2. During classification, the LTC4259A-1 controls and measures the port voltage through the DETECT n pin. Note that class 4 is presently specified by the IEEE as reserved for future ...
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LTC4259A APPLICATIO S I FOR ATIO current to charge its bypass capacitance, slowing the rate of port voltage increase. Dual-Level Current Limit permitted to draw up to 15.4W continuously and up to 400mA for 50ms. ...
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U U APPLICATIO S I FOR ATIO The t timer also implements the duty cycle protec- START tion described under t timing and its duration can be ICUT programmed via register 16h, bits 5 and 4 (Table 1). Foldback Foldback ...
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LTC4259A APPLICATIO S I FOR ATIO The LTC4259A-1 implements foldback to reduce the cur- rent limit when the MOSFET V is high; see the Foldback DS section. Without foldback, the MOSFET could see as much as 25.7W for ...
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U U APPLICATIO S I FOR ATIO DC DISCONNECT DC disconnect monitors the sense resistor voltage when- ever the power make sure that the PD is drawing the minimum specified current. The disconnect timer counts up whenever ...
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LTC4259A APPLICATIO S I FOR ATIO the port impedance. The 1k resistor, R flowing through this path during port power on and power off. Sizing of capacitors is critical to ensure proper function of AC disconnect. C (Figure ...
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U U APPLICATIO S I FOR ATIO Assumimg that f is 100Hz, the 0.1µ OSCIN 0.05µF of cable capacitance gives a port impedance of 10k at 100Hz. The PD AC signature resistance is about 25k. Connecting a PD ...
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LTC4259A APPLICATIO S I FOR ATIO powered ports with AC disconnect enabled (and DC dis- connect not enabled) will automatically disconnect. After the LTC4259A-1 is reset (by power on, Reset All bit or the RESET pin) the Osc ...
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U U APPLICATIO S I FOR ATIO V CPU DD SCL SDA TO CONTROLLER SMBALERT GND CPU U1: FAIRCHILD NC7WZ17 U2, U3: AGILENT HCPL-063L W U 0.1µF U2 200Ω U1 200Ω HCPL-063L U3 200Ω 200Ω 0.1µF HCPL-063L ISOLATED 3.3V + ...
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LTC4259A APPLICATIO S I FOR ATIO direction. A STOP condition is not used to set up a REPEATED START condition, for this would clear any data already latched in. When the master has finished commu- nicating with the ...
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U U APPLICATIO S I FOR ATIO 2 time using standard I C bus arbitration. If the LTC4259A sending a 1 and reads the SDAIN pin on the rising edge of SCL, it assumes another ...
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LTC4259A APPLICATIO S I FOR ATIO ISOLATED 910k GND + 1µF 100V CMPZ4702B V EE 10Ω ISOLATED –48V LOGIC LEVEL SUPPLY In additon to the 48V used to source power to each port, a logic level supply is ...
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U U APPLICATIO S I FOR ATIO and I . Therefore, to maintain IEEE compli- LIM CUT MIN ance, use a resistor with 0.5% or better accuracy. Power MOSFETs The LTC4259A-1 controls power MOSFETs in order to ...
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LTC4259A APPLICATIO S I FOR ATIO Also, C may be important to the voltage stability of a PSE powered port. Port voltage instability is generally not a problem the –48V supply, is well bypassed. For ...
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... MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights Package 36-Lead Plastic SSOP (Wide .300 Inch) ...
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... D AC S1B CONNECTOR 1/2 PULSE H2009 0.01µF 0.01µF 200V 200V 75Ω 75Ω T1 1:1 0.01µF 0.01µF 200V 200V 75Ω 75Ω T1 1000pF 1:1 2000V LT/LWI 1006 REV A • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 2005 L1 RJ45 4258 F22A 4259a1fa ...