ltc4259a Linear Technology Corporation, ltc4259a Datasheet
ltc4259a
Available stocks
Related parts for ltc4259a
ltc4259a Summary of contents
Page 1
... Sourcing Equipment (PSE). It consists of four independent ports, each with output current limit, short-circuit protec- tion, complete Powered Device (PD) detection and classi- fication capability, and programmable PD disconnect using sensing. Used with power MOSFETs and passives as in Figure 1, the LTC4259A can implement a complete IEEE 802.3af-compliant PSE ...
Page 2
... SENSE n ................................. V OUT n .................................... V OSCIN .......................... DGND – 0.3V to DGND + 5V BYP Current .................................................... ±1mA Operating Ambient Temperature Range LTC4259AC ............................................. 0°C to 70°C Junction Temperature (Note 5) ............................ 150°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C ELECTRICAL CHARACTERISTICS temperature range, otherwise specifications are at T (Note 6) ...
Page 3
... Time to Measure PD Signature Resistance (Figure 2) From Successful Detect in Auto or Semiauto Mode to Class Complete From Classify Command in Manual Mode (Figure 2) (Figure 2) From Valid Detect to Port On in Auto Mode (Figure 2) From Port On Command to GATE Pin Current = I (Note 10) LTC4259A = 3.3V –48V unless otherwise noted DD EE MIN TYP MAX ● ...
Page 4
... Figure 6 (Notes 11, 12) Figure 6 (Notes 11, 12) Figure 6 (Notes 11, 12) Figure 6 (Notes 11, 12) (Notes 11, 12, 13) (Notes 11, 12, 13) (Notes 11, 12) Note 7: The LTC4259A is designed to maintain a port voltage of –46.6V to –57V. The V EE diode, MOSFET and sense resistor. Note 8: V supply current, while classifying a short, is measured EE indirectly by measuring the DETECT n pin current while classifying a short ...
Page 5
... PORT VOLTAGE WITH TYPICAL CMPD3003 –16 –18 PIN VOLTAGE – CLASSIFICATION CURRENT (mA) 4258 G05 LTC4259A Powering On a 180µF Load –48V GND EE PORT GATE +14V FET ON LOAD FULLY V EE ...
Page 6
... LTC4259A W U TEST PORT GATE n INT Figure 2. Detect, Class and Turn-On Timing in Auto or Semiauto Modes V SENSE n V SENSE n V MIN INT t VMIN Figure 4. DC Disconnect Timing SCL t 2 SDA INSERTED t DET V CLASS EE t CLSDLY t t DETDLY ...
Page 7
... Figure 9. Reading the Interrupt Register (Short Form R/W ACK AD3 ACK BY SLAVE FRAME 1 FRAME 2 ALERT RESPONSE ADDRESS BYTE SERIAL BUS ADDRESS BYTE Figure 10. Reading from Alert Response Address LTC4259A ACK ACK BY STOP BY SLAVE MASTER FRAME 3 DATA BYTE 4259A F07 R/W ACK D7 ...
Page 8
... CTIO S RESET (Pin 1): Chip Reset, Active Low. When the RESET pin is low, the LTC4259A is held inactive with all ports off and all internal registers reset to their power-up states. When RESET is pulled high, the LTC4259A begins normal operation. RESET can be connected to an external capaci- tor or RC network to provide a power turn-on delay ...
Page 9
... GATE1 (Pin 33): Port 1 Gate Drive. See GATE 4. OUT1 (Pin 34): Port 1 Output Voltage Monitor. See OUT4. AUTO (Pin 35): Auto Mode Input. Auto mode allows the LTC4259A to detect and power even if there is no host controller present on the I AUTO pin determines the state of the internal registers when the LTC4259A is reset or comes out of V (see the Register map in Table 1) ...
Page 10
... LTC4259A W TABLE 1. REGISTER AP 10 4259afb ...
Page 11
... Interrupt register as the Class Com- plete bit. In Manual mode, this register indicates that the requested detection/classification cycle has completed and the LTC4259A is awaiting further instructions. In Semiauto or Auto modes, these bits indicate that the Detect Status and Class Status bits in the Port Status registers are valid. ...
Page 12
... Operating Mode (Address 12h): Operating Mode Configu- ration, Read/Write. This register contains the mode bits for each of the four ports in the LTC4259A. See Table 1 for mode bit encoding. At power-up, all bits in this register will be set to the logic state of the AUTO pin (Pin 35). See Operating Modes in the Applications Information section ...
Page 13
... OSCIN pin from setting the Osc Fail bit and causing a Supply Event Interrupt. Setting bit 7 enables the INT pin. If this bit is reset, the LTC4259A will not pull down the INT pin in any condition nor will it respond to the Alert Response Address. This bit is set by default. ...
Page 14
... LTC4259A U U REGISTER FU CTIO S way, the condition causing the LTC4259A to pull the INT pin down must be removed before the LTC4259A will be able to pull INT down again. This can be done by reading and clearing the event registers or by writing a 1 into bit ...
Page 15
... C Power Off bit in the Power Enable PB register. Power-On RESET At turn-on or any time the LTC4259A is reset (either by pulling the RESET pin low or writing to the global Reset All bit), all the ports turn off and all internal registers predefined state, shown in Table 1. ...
Page 16
... W U The LTC4259A will not report Detect Good if the PD has more than 5µF in parallel with its signature resistor. The port’s operating mode controls if and when the LTC4259A runs a detection cycle. In manual mode, the port will sit idle until a Restart Detection (register 18h) command is received ...
Page 17
... F14 maintain consistency with the standard, the I is used when referring to an initial t When the LTC4259A turns on a port, it turns on the MOSFET by pulling up on the gate. The LTC4259A is designed to power up the port in current limit, limiting the inrush current to I ...
Page 18
... LTC4259A U U APPLICATIO S I FOR ATIO Dual-Level Current Limit permitted to draw up to 15.4W continuously and up to 400mA for 50ms. The LTC4259A has two correspond- ing current limit thresholds, I (375mA typ) and I CUT (425mA typ). These are given by the equations ...
Page 19
... With 0.5Ω sense resistors, this limits the short-circuit current to 60mA (typ) instead of the full 425mA (typ) current limit. When the LTC4259A is in foldback, the t timer is active. ICUT ...
Page 20
... LTC4259A to normal operating mode. A substantial transient surge suppressor can typically protect the LTC4259A and the rest of the PSE from these faults. Placing a polyfuse between the RJ-45 connector and the LTC4259A and its associated circuitry can provide additional protection. To meet safety requirements, place the polyfuse in the ground leg of the PSE’ ...
Page 21
... AC DISCONNECT AC disconnect is an alternate method of sensing the pres- ence or absence monitoring the port impedance. The LTC4259A forces a signal, amplified from the OSCIN pin, out of the DETECT pins and onto the Power over Eth- ernet connection. It calculates the connection impedance from ohm’ ...
Page 22
... PD only makes a 20% reduction in the port impedance requiring the AC disconnect circuitry to be quite sensitive. When the OSCIN pin is driven with a sine wave, the LTC4259A is able to distinguish between capaci- tive impedance and resistive impedance on the Power over Ethernet connection. AC disconnect is reliable for cable capacitance up to about 0.2µ ...
Page 23
... When the OSCIN signal is either absent or corrupted, powered ports with AC disconnect enabled (and DC dis- connect not enabled) will automatically disconnect. After the LTC4259A is reset (by power on, Reset All bit or the has RESET pin) the Osc Fail bit is set. Once the Osc Fail bit is ...
Page 24
... If the SDA and SCL pull-ups are absent, not con- nected to the same positive supply as the LTC4259A’s V pin, or are not activated when the power is applied to the LTC4259A possible for the LTC4259A to see a START 2 condition on the I C bus. The interrupt pin (INT) is only ...
Page 25
... BYP 0.1µF 0.1µF LTC4259A V DD INT SCL SDAIN SDAOUT AD0 AD1 AD2 AD3 DGND AGND BYP 0.1µF • 0.1µF • • LTC4259A V DD INT SCL SDAIN SDAOUT AD0 AD1 AD2 AD3 DGND AGND BYP 0.1µF 0.1µF LTC4259A V DD INT SCL SDAIN ...
Page 26
... LTC4259A initiated the interrupt. The master initiates the ARA procedure with a START condition and the 7-bit ARA bus address (0001100)b followed by the Read Bit (Rd LTC4259A is asserting the INT pin, it acknowledges and sends its 7-bit bus address (010A ...
Page 27
... In a typical PSE, the LTC4259As will operate in Semiauto mode as this allows the controller to decide to power a port without unduly burdening the controller. With an interrupt mask of F4h, the LTC4259A will signal to the host after it has successfully detected and classed a PD, at which point the host can decide whether enough power is available and command the LTC4259A to turn that port on ...
Page 28
... LTC4259A in a PSE does not guarantee 802.3af compliance. Using an LTC4259A does get you most of the way there. This section discusses the rest of the elements that go along with the LTC4259A to make an 802.3af complaint PSE. Each paragraph below addresses a com- ponent which is critical for PSE compliance as well as possible pitfalls that can cause a PSE to be noncompliant. For further assistance please contact Linear Technology’ ...
Page 29
... The LTC4259A must be supplied with 3.3V (V –48V (V EE can lead to noncompliance. The IEEE requires a PSE output voltage between 44V and 57V. When the LTC4259A begins powering an Ethernet port, it controls the current through the port to minimize disturbances on V ever, if the V unstable, its voltage could go outside of the IEEE specified limits, causing all ports in the PSE to be noncompliant ...
Page 30
... Out-of-band noise on the OSCIN pin will disrupt the LTC4259A’s ability to sense the absence of a PD. Any noise present at the OSCIN pin is amplified by the LTC4259A and driven out of the DETECT pins (of powered ports with AC disconnect enabled). Due to the amount of capacitance ...
Page 31
... DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE LTC4259A 15.290 – 15.544* (.602 – .612) 10.160 – 10.414 (.400 – .410) 2.286 – ...
Page 32
... Linear Technology Corporation 32 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 ● ISOLATED 3.3V 0.1µF OSCIN DGND AGND SCL 1/4 SDAIN LTC4259A SDAOUT INT V SENSE GATE OUT EE 2k 0.1µ 0.5Ω Q1 –48V IRFM120A ISOLATED U3 200Ω 200Ω PHY ...