WM8903LGEFK/V Wolfson Microelectronics, WM8903LGEFK/V Datasheet - Page 88

• Manufacturer Part Number: WM8903LGEFK/V
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/V

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8903
w
Sample rate setting for 48kHz
CONTROL INTERFACE CLOCKING
In certain configurations, such as analog bypass to differential line outputs, WM8903 can be used
without MCLK (compared to LINEOUTL/R, which requires the charge pump hence requires MCLK).
Without MCLK applied, CLK_SYS_ENA should be left in its default state otherwise there is limited
access to the register map as detailed in Table 58.
Table 58 Serial Interface Access with CLK_SYS_ENA and MCLK
DAC SETUP
For correct DAC functionality with sample rates up to 48kHz, one of the following CLK_SYS limits
must be observed, depending on the setting of the DAC_MONO and DAC_OSR register bits. See
“Digital to Analogue Converter (DAC)” for definitions of DAC_MONO and DAC_OSR.
DAC_MONO = 0
DAC_MONO = 0
DAC_MONO = 1
DAC_MONO = 1
Table 59 Minimum CLK_SYS for DAC Operation
For correct DAC functionality with 88.2kHz or 96kHz sample rates, and if the ADC is not configured,
125 x fs or 128 x fs must be selected, or in the case of 88.2kHz, 136 x fs can also be selected. The
correct setting of SAMPLE_RATE should be selected (i.e. 1001 or 1010). The CLK_SYS frequency
should not exceed the limitations stated in the “Signal Timing Requirements” section.
For best DAC noise performance, CLK_SYS ≥ 3MHz. (Note that there is no equivalent condition for
ADC noise performance.)
ADC SETUP
For correct ADC functionality with sample rates up to 48kHz, it must be ensured that CLK_SYS ≥
256 x fs. At 48kHz, if ADC_OSR = 0, it must be ensured that CLK_SYS
For correct ADC functionality with 88.2kHz or 96kHz sample rates, CLK_SYS must equal 128 x fs,
and the SAMPLE_RATE register should be set for half the required sample rate. For example,
Table 60 Clock Settings for ADC at 96kHz Sample Rate
Configuring the ADC for 88.2kHz requires the same settings as detailed in Table 60, except that
SAMPLE_RATE should be set to 44.1kHz (0111).
The CLK_SYS frequency should not exceed the limitations stated in the “Signal Timing
Requirements” section.
Simultaneous ADC and DAC operation at 88.2kHz or 96kHz sample rates is not possible, but ADC
and DAC can both be set up to the required sample rates, then selected alternately using the
DACL_ENA, DACR_ENA, ADCL_ENA, ADCR_ENA.
shows the settings required for 96kHz ADC sample rate.
MCLK PRESENT
BCLK = CLK_SYS / 2
CLK_SYS = 128 x fs
LRCLK = BCLK / 64
CONDITION
Yes
No
No
CONDITIONS
CLK_SYS_ENA
DAC_OSR = 0
DAC_OSR = 1
DAC_OSR = 0
DAC_OSR = 1
Don’t care
0 (default)
1
CLK_SYS_MODE
CLK_SYS_RATE
REGISTER BITS
SAMPLE_RATE
LRCLK_RATE
BCLK_DIV
R22 (TO ADJUST
CLK_SYS_ENA)
CLK_SYS ≥ 128 x fs
CLK_SYS ≥ 256 x fs
CLK_SYS ≥ 64 x fs
CLK_SYS ≥ 128 x fs
Yes
Yes
Yes
REGISTER ACCESS
CLK_SYS
000_0100_0000
SETTING
0_0010
ALL OTHER
REGISTERS
0001
1000
PP, Rev 3.1, August 2009
00
128 x fs.
Yes
Yes
No
Pre-Production
88