WM8734SEFL Wolfson Microelectronics, WM8734SEFL Datasheet - Page 23

• Manufacturer Part Number: WM8734SEFL
• Description: Audio CODECs Stereo CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8734SEFL

• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-28
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8734
Figure 16 Left Justified Mode
Figure 17 I
w
DACLRC/
DACLRC/
ADCLRC
ADCLRC
DACDAT/
DACDAT/
ADCDAT
ADCDAT
BCLK
BCLK
2
S Mode
MSB
1
MSB
1 BCLK
2
1
The digital audio interface takes the data from the internal ADC digital filter and places it on the
ADCDAT output. ADCDAT is the formatted digital audio data stream output from the ADC digital
filters with left and right channels multiplexed together. ADCLRC is an alignment clock that controls
whether Left or Right channel data is present on the ADCDAT lines. ADCDAT and ADCLRC are
synchronous with the BCLK signal with each data bit transition signified by a BCLK high to low
transition. BCLK maybe an input or an output dependent on whether the device is in master or slave
mode. Refer to the MASTER/SLAVE OPERATION section.
The digital audio interface also receives the digital audio data for the internal DAC digital filters on the
DACDAT input. DACDAT is the formatted digital audio data stream output to the DAC digital filters
with left and right channels multiplexed together. DACLRC is an alignment clock that controls
whether Left or Right channel data is present on DATDAT. DACDAT and DACLRC are synchronous
with the BCLK signal with each data bit transition signified by a BCLK transition. DACDAT is always
an input. BCLK and DACLRC are either outputs or inputs depending whether the device is in master
or slave mode. Refer to the MASTER/SLAVE OPERATION section
There are four digital audio interface formats accommodated by the WM8734. These are shown in
the figures below. Refer to the Electrical Characteristic section for timing information.
Left Justified mode is where the MSB is available on the first rising edge of BCLK following a ADCLR
or DACLRC transition.
I
ADCLRC transition.
Right Justified mode is where the LSB is available on the rising edge of BCLK preceding a DACLRC
or ADCLRC transition, yet MSB is still transmitted first.
2
3
2
S mode is where the MSB is available on the 2
3
LEFT CHANNEL
LEFT CHANNEL
n-2 n-1
n-2 n-1
n
LSB
n
LSB
MSB
1/fs
1/fs
1
MSB
1 BCLK
2
1
3
2
nd
rising edge of BCLK following a DACLRC or
3
RIGHT CHANNEL
RIGHT CHANNEL
n-2 n-1
n-2 n-1
PD, Rev 4.3, January 2009
n
LSB
n
LSB
Production Data
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