SL28SRC02BZI Silicon Laboratories Inc, SL28SRC02BZI Datasheet

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SL28SRC02BZI

Manufacturer Part Number
SL28SRC02BZI
Description
Clock Generators & Support Products PCIE Clk Gen Xin 14M -->4 PCIE out Gen3
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of SL28SRC02BZI

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Rev 1.1 November 9, 2009
2200 Laurelwood Road, Santa Clara, CA 95054
Features
• Low power PCI Express Gen 2 & Gen 3 clock generator
• Two100-MHz differential SRC clocks
• Low power push-pull output buffers (no 50ohm to
• Integrated 33ohm series termination resistors
• Low jitter (<50pS)
ground needed)
14.318MHz
crystal or clock
SSON
Block Diagram
Control
logic
Crystal
Oscillator/
clock buffer
PCI Express Gen 2 & Gen 3 Clock Generator
PLL
Tel:(408) 855-0555
• SSON input for enabling spread spectrum clock
• I
• Triangular Spread Spectrum profile for maximum
• Input frequency of 14.318MHz
• Industrial Temperature -40
• 3.3V power supply
• 20-pin TSSOP package
SRC1
SRC1#
SRC2
SRC2#
electromagnetic interference (EMI) reduction
2
C support with readback capabilities
Fax:(408) 855-0550
SDATA 2
SRC1# 9
SRC1 8
SCLK 3
Pin Configuration
VDD 1
VDD 4
VDD 6
VSS 5
VSS 7
VSS 10
o
SL28SRC02
C to 85
www.SpectraLinear.com
20 XIN
19 XOUT
18 VSS
17 SSON
16 VDD
15 VSS
14 VDD
13 VDD
12 SRC2#
11 SRC2
o
C
Page 1 of 14

Related parts for SL28SRC02BZI

SL28SRC02BZI Summary of contents

Page 1

PCI Express Gen 2 & Gen 3 Clock Generator Features • Low power PCI Express Gen 2 & Gen 3 clock generator • Two100-MHz differential SRC clocks • Low power push-pull output buffers (no 50ohm to ground needed) • Integrated ...

Page 2

Pin Definitions Pin No. Name Type 1 VDD PWR 2 SDATA 3 SCLK 4 VDD PWR 5 VSS GND 6 VDD PWR 7 VSS GND 8 SRC1 O, DIF 100 MHz Differential serial reference clocks. 9 SRC1# O, DIF 100 ...

Page 3

Table 2. Block Read and Block Write Protocol Block Write Protocol Bit Description 1 Start 8:2 Slave address–7 bits 9 Write 10 Acknowledge from slave 18:11 Command Code–8 bits 19 Acknowledge from slave 27:20 Byte Count–8 bits 28 Acknowledge from ...

Page 4

Control Registers Byte 0: Control Register 0 Bit @Pup Name 7 HW RESERVED 6 0 RESERVED 5 1 RESERVED 4 0 RESERVED 3 0 RESERVED 2 0 RESERVED 1 0 RESERVED 0 1 RESERVED Byte 1: Control Register 1 Bit ...

Page 5

Byte 4: Control Register 4 Bit @Pup Name 7 1 RESERVED 6 1 SRC1_OE 5 1 SRC2_OE 4 1 RESERVED 3 1 RESERVED 2 1 RESERVED 1 1 PLL1_SS_EN 0 1 RESERVED Byte 5: Control Register 5 Bit @Pup Name ...

Page 6

Byte 8: Control Register 8 Bit @Pup Name 7 1 Device_ID3 6 0 Device_ID2 5 0 Device_ID1 4 0 Device_ID0 3 0 RESERVED 2 0 RESERVED 1 1 RESERVED 0 1 RESERVED Byte 9: Control Register 9 Bit @Pup Name ...

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Byte 11: Control Register 11 (continued RESERVED 1 1 PCI-E_GEN2 0 1 RESERVED Byte 12: Byte Count Bit @Pup Name 7 0 BC7 6 0 BC6 5 0 BC5 4 0 BC4 3 1 BC3 2 1 BC2 ...

Page 8

Table 4. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap 14.31818 MHz AT Parallel The SL28SRC02 requires a Parallel Resonance Crystal. Substituting a series resonance SL28SRC02 to operate at the wrong frequency and violates the ppm specification. For most applications ...

Page 9

Absolute Maximum Conditions Parameter Description V Core Supply Voltage DD V Input Voltage IN T Temperature, Storage S T Temperature, Operating A Ambient T Temperature, Junction J Ø Dissipation, Junction to Case JC Ø Dissipation, Junction to Ambient JEDEC (JESD ...

Page 10

AC Electrical Specifications Parameter Description Crystal T XIN Duty Cycle DC T XIN Period PERIOD T /T XIN Rise and Fall Times XIN Cycle to Cycle Jitter CCJ SRC T SRC Duty Cycle DC T 100 MHz ...

Page 11

Test and Measurement Set-up For SRC Signals This diagram shows the test load configuration for the differential SRC outputs Figure 4. Differential Measurement for Differential Output Signals (for AC Parameters Measurement) Rev 1.1 Figure 3. 0.7V Differential Load Configuration SL28SRC02 ...

Page 12

... Vcross median CLK Figure 5. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement) Ordering Information Part Number Lead-free SL28SRC02BZI 20-pin TSSOP SL28SRC02BZIT 20-pin TSSOP–Tape and Reel SL 28 SRC02 This device is Pb free and RoHS compliant Rev 1.1 = 1.15V V = 1.15V MAX = 0 ...

Page 13

Package Diagrams Rev 1.1 20-pin TSSOP SL28SRC02 Page ...

Page 14

Document History Page Document Title: SL28SRC02 PCI Express Gen 2 & Gen 3 Clock Generator Orig. of REV. Issue Date Change 1.0 10/28/09 JMA New Datasheet 1.1 11/06/09 JMA Updated Figure 4 While SpectraLinear Inc. has reviewed all information herein ...

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